LDC1 110101 |
base |
ft |
offset |
6 |
5 |
5 |
16 |
LDC1 ft, offset(base) |
MIPS32 |
Load Doubleword to Floating Point |
Load Doubleword to Floating Point
To load a doubleword from memory to an FPR.
FPR[ft] = memory[GPR[base] + offset]
The contents of the 64-bit doubleword at the memory location specified by the aligned effective address are fetched and placed in FPR ft. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
Pre-Release 6: An Address Error exception occurs if EffectiveAddress2..0 != 0 (not doubleword-aligned).
Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.
Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.
vAddr = sign_extend(offset) + GPR[base] (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD) memdoubleword = LoadMemory(CCA, DOUBLEWORD, pAddr, vAddr, DATA) paddr = paddr xor ((BigEndianCPU xor ReverseEndian) || 02) memlsw = LoadMemory(CCA, WORD, pAddr, vAddr, DATA) paddr = paddr xor 0b100 memmsw = LoadMemory(CCA, WORD, pAddr, vAddr+4, DATA) memdoubleword = memmsw || memlsw StoreFPR(ft, UNINTERPRETED_DOUBLEWORD, memdoubleword)
Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, Address Error, Watch