Encoding:

pre-Release 6

Release 6

Format:

LDC2 rt, offset(base)

Purpose:

Load Doubleword to Coprocessor 2

To load a doubleword from memory to a Coprocessor 2 register.

Description:

 CPR[2,rt,0] = memory[GPR[base] + offset]

The contents of the 64-bit doubleword at the memory location specified by the aligned effective address are fetched and placed in Coprocessor 2 register rt. The signed offset is added to the contents of GPR base to form the effective address.

Restrictions:

Pre-Release 6: An Address Error exception occurs if EffectiveAddress_2..0 != 0 (not doubleword-aligned).

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Availability and Compatibility:

This instruction has been recoded for Release 6.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memdoubleword = LoadMemory(CCA, DOUBLEWORD, pAddr, vAddr, DATA)
CPR[2,rt,0] = memdoubleword
paddr = paddr xor ((BigEndianCPU xor ReverseEndian) || 02)
memlsw = LoadMemory(CCA, WORD, pAddr, vAddr, DATA)
paddr = paddr xor 0b100
memmsw = LoadMemory(CCA, WORD, pAddr, vAddr+4, DATA)
=memlsw
memmsw

Exceptions:

Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, Address Error, Watch

Programming Notes:

There is no Load Linked Word Unsigned operation corresponding to Load Word Unsigned.

Release 6 implements a 9-bit offset, whereas all release levels lower than Release 6 implement a 16-bit offset.

Programming Notes:

As shown in the instruction drawing above, Release 6 implements an 11-bit offset, whereas all release levels lower than Release 6 of the MIPS architecture implement a 16-bit offset.