|
COP0 010000 |
MFH 00010 |
rt |
rd |
0 00000000 |
sel |
|
6 |
5 |
5 |
5 |
8 |
3 |
MFHC0 rt, rd, sel |
MIPS32 Release 5 |
Move from High Coprocessor 0 |
Move from High Coprocessor 0
To move the contents of the upper 32 bits of a Coprocessor 0 register, extended by 32-bits, to a general register.
GPR[rt] = CPR[0,rd,sel][63:32]
The contents of the Coprocessor 0 register specified by the combination of rd and sel are sign-extended and loaded into general register rt. Not all Coprocessor 0 registers support the sel field, and in those instances, the sel field must be zero.
When the Coprocessor 0 register specified is the EntryLo0 or the EntryLo1 register, MFHC0 must undo the effects of
MTHC0, that is, bits 31:30 of the register must be returned as bits 1:0 of the GPR, and bits 32 and those of greater significance must be left-shifted by two and written to bits 31:2 of the GPR. This is because the RI and XI bits are repositioned on the write from GPR to EntryLo0 or the EntryLo1.
Pre-Release 6: The results are UNDEFINED if Coprocessor 0 does not contain a register as specified by rd and sel, or the register exists but is not extended by 32-bits, or the register is extended for XPA, but XPA is not supported or enabled.
Release 6: Reading the high part of a register that is reserved, not implemented for the current core configuration, or that is not extended beyond 32 bits returns 0.
This feature supports MIPS32 backward-compatibility on MIPS64 implementations.
PABITS is the total number of physical address bits implemented. PABITS is defined in the descriptions of EntryLo0 and EntryLo1.
if Config5MVH = 0 then SignalException(ReservedInstruction) endif
reg = rd
if IsCoprocessorRegisterImplemented(0, reg, sel) and
IsCoprocessorRegisterExtended(0, reg, sel) then
data = CPR[0, reg, sel]
if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
if (Config3LPA = 1 and PageGrainELPA = 1) then // PABITS > 36
GPR[rt]31..0 = data61..30
GPR[rt]63..32 = (data61)32 // sign-extend
else
GPR[rt] = 0
endif
else
GPR[rt] = sign_extend(data63..32)
endif
else
if ArchitectureRevision() >= 6 then
GPR[rt] = 0
else
UNDEFINED
endif
endif
Coprocessor Unusable, Reserved Instruction