Encoding:

Format:

LUXC1 fd, index(base)

Purpose:

Load Doubleword Indexed Unaligned to Floating Point

To load a doubleword from memory to an FPR (GPR+GPR addressing), ignoring alignment

Description:

 FPR[fd] = memory[(GPR[base] + GPR[index])PSIZE-1..3]

The contents of the 64-bit doubleword at the memory location specified by the effective address are fetched and placed into the low word of FPR fd. The contents of GPR index and GPR base are added to form the effective address. The effective address is doubleword-aligned; EffectiveAddress2..0 are ignored.

Restrictions:

The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model; it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.

Availability and Compatibility:

This instruction has been removed in Release 6.

Operation:

vAddr = (GPR[base]+GPR[index])63..3 || 03
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memdoubleword  LoadMemory(CCA, DOUBLEWORD, pAddr, vAddr, DATA)
paddr = paddr xor ((BigEndianCPU xor ReverseEndian) || 02)
memlsw = LoadMemory(CCA, WORD, pAddr, vAddr, DATA)
paddr = paddr xor 0b100
memmsw = LoadMemory(CCA, WORD, pAddr, vAddr+4, DATA)
memdoubleword = memmsw || memlsw
StoreFPR(ft, UNINTERPRETED_DOUBLEWORD, memdoubleword)

Exceptions:

Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, Watch