Encoding:

COP1X

010011

base

index

fs

0

00000

SWXC1

001000

6

5

5

5

5

6

Format: 

SWXC1 fs, index(base)

MIPS64, MIPS32 Release 2, removed in Release 6

Store Word Indexed from Floating Point

Purpose:

Store Word Indexed from Floating Point

To store a word from an FPR to memory (GPR+GPR addressing)

Description: 

 memory[GPR[base] + GPR[index]] = FPR[fs]

The low 32-bit word from FPR fs is stored in memory at the location specified by the aligned effective address. The contents of GPR index and GPR base are added to form the effective address.

Restrictions:

An Address Error exception occurs if EffectiveAddress1..0 != 0 (not word-aligned).

Availability and Compatibility:

This instruction has been removed in Release 6.

Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32 Release 1. Required in

MIPS32 Release 2 and all subsequent versions of MIPS32. When required, required whenever FPU is present, whether a 32-bit or 64-bit FPU, whether in 32-bit or 64-bit FP Register Mode (FIRF64=0 or 1, StatusFR=0 or 1).

Operation: 

vAddr = GPR[base] + GPR[index]
if vAddr1..0 != 03 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation(vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
bytesel = vAddr2..0 xor (BigEndianCPU || 02)
datadoubleword = ValueFPR(fs, UNINTERPRETED_WORD) || 08*bytesel
StoreMemory(CCA, WORD, datadoubleword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Address Error, Reserved Instruction, Coprocessor Unusable, Watch