BC 110010 |
offset |
6 |
26 |
BC offset |
MIPS32 Release 6 |
Branch, Compact |
Branch, Compact
PC = PC+4 + sign_extend( offset << 2)
A 28-bit signed offset (the 26-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.
Compact branches have no delay slot: the instruction after the branch is NOT executed when the branch is taken.
This instruction is an unconditional, always taken, compact branch. It does not have a forbidden slot, that is, a
Reserved Instruction exception is not caused by a Control Transfer Instruction placed in the slot following the branch.
This instruction is introduced by and required as of Release 6.
Release 6 instruction BC occupies the same encoding as pre-Release 6 instruction LWC2. The LWC2 instruction has been moved to the COP2 major opcode in MIPS Release 6.
None
target_offset = sign_extend( offset || 02 ) PC = ( PC+4 + sign_extend(target_offset) )