Encoding:

MSA

011110

00001

wt

ws

wd

VEC

011110

6

5

5

5

5

6

Format: 

OR.V

Vector Logical Or

OR.V wd,ws,wt

MSA

Vector Logical Or

Purpose:

Vector Logical Or

Vector by vector logical or.

Description: 

wd = ws OR wt

Each bit of vector ws is combined with the corresponding bit of vector wt in a bit wise logical OR operation. The result is written to vector wd.

The operands and results are bit vector values.

Restrictions:

No data-dependent exceptions are possible.

Operation: 

 WR[wd] = WR[ws] or WR[wt]

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.