Encoding:

Format:

SLL.df 

SLL.B wd,ws,wt

SLL.H wd,ws,wt

SLL.W wd,ws,wt

SLL.D wd,ws,wt

Purpose:

Vector Shift Left

Vector bit count shift left.

Description:

wd[i] = ws[i] << wt[i]

The elements in vector ws are shifted left by the number of bits the elements in vector wt specify modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

SLL.B
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = WR[ws]8i+8-t-1..8i || 0t
   endfor
SLL.H
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = WR[ws]16i+16-t-1..16i || 0t
   endfor
SLL.W
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = WR[ws]32i+32-t-1..32i || 0t
   endfor
SLL.D
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = WR[ws]64i+64-t-1..64i || 0t
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.