Encoding:

MSA

011110

00010

wt

ws

wd

VEC

011110

6

5

5

5

5

6

Format: 

NOR.V

Vector Logical Negated Or

NOR.V wd,ws,wt

MSA

Vector Logical Negated Or

Purpose:

Vector Logical Negated Or

Vector by vector logical negated or.

Description: 

wd = ws NOR wt

Each bit of vector ws is combined with the corresponding bit of vector wt in a bi twise logical NOR operation. The result is written to vector wd.

The operands and results are bit vector values.

Restrictions:

No data-dependent exceptions are possible.

Operation: 

 WR[wd] = WR[ws] nor WR[wt]

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.