Encoding:

Format:

SRL.df 

SRL.B wd,ws,wt

SRL.H wd,ws,wt

SRL.W wd,ws,wt

SRL.D wd,ws,wt

Purpose:

Vector Shift Right Logical

Vector bit count shift right logical.

Description:

wd[i] = ws[i] >> wt[i]

The elements in vector ws are shifted right logical by the number of bits the elements in vector wt specify modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

SRL.B
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = 0t || WR[ws]8i+7..8i+t
   endfor
SRL.H
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = 0t || WR[ws]16i+15..16i+t
   endfor
SRL.W
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = 0t || WR[ws]32i+31..32i+t
   endfor
SRL.D
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = (WR[ws]64i+63)t || WR[ws]64i+63..64i+t
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.