|
POP10 001000 |
BOVC rs >= rt rs |
rt |
offset |
|
POP30 011000 |
BNVC rs >= rt rs |
rt |
offset |
|
6 |
5 |
5 |
16 |
BOVC BNVC |
Detect overflow for add (signed 32 bits) and branch if overflow. | |
BOVC rs,rt,offset |
MIPS32 Release 6 |
Detect overflow for add (signed 32 bits) and branch if overflow. |
BNVC rs,rt,offset |
MIPS32 Release 6 |
Detect overflow for add (signed 32 bits) and branch if no overflow. |
Branch on Overflow, Compact; Branch on No Overflow, Compact
BOVC: Detect overflow for add (signed 32 bits) and branch if overflow.
BNVC: Detect overflow for add (signed 32 bits) and branch if no overflow.
branch if/if-not NotWordValue(GPR[rs]+GPR[rt])
BOVC performs a signed 32-bit addition of rs and rt. BOVC discards the sum, but detects signed 32-bit integer overflow of the sum (and the inputs, in MIPS64), and branches if such overflow is detected.
BNVC performs a signed 32-bit addition of rs and rt. BNVC discards the sum, but detects signed 32-bit integer overflow of the sum (and the inputs, in MIPS64), and branches if such overflow is not detected.
BOVC and BNVC are compact branches-they have no branch delay slots, but do have a forbidden slot.
A 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.
On 64-bit processors, BOVC and BNVC detect signed 32-bit overflow on the input registers as well as the output.
This checking is performed even if 64-bit operations are not enabled.
The special case with rt=0 (for example, GPR[0]) is allowed. On MIPS64, this checks that the input value of rs is a well-formed signed 32-bit integer: BOVC rs,r0,offset branches if rs is not a 32-bit integer, and BNVC rs, r0 offset branches if rs is a 32-bit integer. On MIPS32, BOVC rs,r0 offset never branches, while BNVC rs,r0 offset always branches.
The special case of rs=0 and rt=0 is allowed. BOVC never branches, while BNVC always branches.
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs
include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
If a control transfer instruction (CTI) is executed in the forbidden slot of a compact branch, Release 6 implementations are required to signal a Reserved Instruction exception, but only when the branch is not taken.
These instructions are introduced by and required as of Release 6.
See section A.4 on page 591 in Volume II for a complete overview of Release 6 instruction encodings. Brief notes related to these instructions:
BOVC uses the primary opcode allocated to MIPS32 pre-Release 6 ADDI. Release 6 reuses the ADDI primary opcode for BOVC and other instructions, distinguished by register numbers.
BNVC uses the primary opcode allocated to MIPS64 pre-Release 6 DADDI. Release 6 reuses the DADDI primary opcode for BNVC and other instructions, distinguished by register numbers.
input_overflow = NotWordValue(GPR[rs]) or NotWordValue(GPR[rt]) temp1 = sign_extend.32( GPR[rs]31..0 ) temp2 = sign_extend.32( GPR[rt]31..0 ) tempd = temp1 + temp2 // wider than 32-bit precision sum_overflow = (tempd32 != tempd31) BOVC: cond = sum_overflow or input_overflow BNVC: cond = not( sum_overflow or input_overflow ) if cond then PC = ( PC+4 + sign_extend( offset << 2 ) ) endif
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