Encoding:

SPECIAL3

011111

ALIGN

010

BSHFL

100000

SPECIAL3

011111

DALIGN

DBSHFL

100100

Format:

ALIGN DALIGN		Concatenate two GPRs, and extract a contiguous subset at a byte position
ALIGN rd,rs,rt,bp	MIPS32 Release 6	Concatenate two GPRs, and extract a contiguous subset at a byte position
DALIGN rd,rs,rt,bp	MIPS64 Release 6	Concatenate two GPRs, and extract a contiguous subset at a byte position

Purpose:

Concatenate two GPRs, and extract a contiguous subset at a byte position

Description:

GPR[rd] = (GPR[rt] << (8*bp)) or (GPR[rs] >> (GPRLEN-8*bp))

The input registers GPR rt and GPR rs are concatenated, and a register width contiguous subset is extracted, which is specified by the byte pointer bp.

The ALIGN instruction operates on 32-bit words, and has a 2-bit byte position field bp.

The DALIGN instruction operates on 64-bit doublewords, and has a 3-bit byte position field bp.

ALIGN: The rightmost 32-bit word in GPR rt is left shifted as a 32-bit value by bp byte positions. The rightmost

32-bit word in register rs is right shifted as a 32-bit value by (4-bp) byte positions. These shifts are logical shifts, zero-filling. The shifted values are then or-ed together to create a 32-bit result that is sign-extended to 64bits and written to destination GPR rd.

DALIGN: The 64-bit doubleword in GPR rt is left shifted as a 64 bit value by bp byte positions. The 64-bit word in register rs is right shifted as a 64-bit value by (8-bp) byte positions. These shifts are logical shifts, zero-filling. The shifted values are then or-ed together to create a 64-bit result and written to destination GPR

rd.

Restrictions:

Executing ALIGN and DALIGN with shift count bp=0 acts like a register to register move operation, and is redundant, and therefore discouraged. Software should not generate ALIGN or DALIGN with shift count bp=0.

DALIGN: A Reserved Instruction exception is signaled if access to 64-bit operations is not enabled.

Availability and Compatibility:

The ALIGN instruction is introduced by and required as of Release 6.

The DALIGN instruction is introduced by and required as of Release 6.

Programming Notes:

Release 6 ALIGN instruction corresponds to the pre-Release 6 DSP Module BALIGN instruction, except that

BALIGN with shift counts of 0 and 2 are specified as being UNPREDICTABLE, whereas ALIGN (and DALIGN) defines all bp values, discouraging only bp=0.

Operation:

ALIGN:
 tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
 tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
 tmp = tmp_rt_hi or tmp_rt_lo
ALIGN on a 32-bit CPU:
 GPR[rd] = tmp
ALIGN on a 64-bit CPU:
 GPR[rd] = sign_extend.32(tmp)
DALIGN:
 if not Are64bitOperationsEnabled()
   then SignalException(ReservedInstruction) endif
 tmp_rt_hi = unsigned_doubleword(GPR[rt]) << (8*bp)
 tmp_rs_lo = unsigned_doubleword(GPR[rs]) >> (8*(8-bp))
 tmp = tmp_rt_hi or tmp_rt_lo
 GPR[rd] = tmp
/* end of instruction */

Exceptions:

ALIGN: None

DALIGN: Reserved Instruction