Encoding:

Format:

LWLE rt, offset(base)

Purpose:

Load Word Left EVA

To load the most-significant part of a word as a signed value from an unaligned user mode virtual address while executing in kernel mode.

Description:

 GPR[rt] = GPR[rt] MERGE memory[GPR[base] + offset]

The 9-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the most-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.

The most-significant 1 to 4 bytes of W is in the aligned word containing the EffAddr. This part of W is loaded into the most-significant (left) part of the word in GPR rt. The remaining least-significant part of the word in GPR rt is unchanged.

For 64-bit GPR rt registers, the destination word is the low-order word of the register. The loaded value is treated as a signed value; the word sign bit (bit 31) is always loaded from memory and the new sign bit value is copied into bits

63..32.

Restrictions:

Only usable when access to Coprocessor0 is enabled and when accessing an address within a segment configured using UUSK, MUSK or MUSUK access mode.

Availability and Compatibility:

Release 6 removes the load/store-left/right family of instructions, and requires the system to support misaligned memory accesses.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor ReverseEndian3)
if BigEndianMem = 0 then
   pAddr = pAddrPSIZE-1..3 || 03
endif
byte = 0 || (vAddr1..0 xor BigEndianCPU2)
word = vAddr2 xor BigEndianCPU
memdoubleword = LoadMemory (CCA, byte, pAddr, vAddr, DATA)
temp = memdoubleword31+32*word-8*byte..32*word || GPR[rt]23-8*byte..0
GPR[rt] = (temp31)32 || temp

Exceptions:

TLB Refill, TLB Invalid, Bus Error, Address Error, Watch, Reserved Instruction, Coprocessor Unusable

Programming Notes:

The architecture provides no direct support for treating unaligned words as unsigned values, that is, zeroing bits

63..32 of the destination register when bit 31 is loaded.

Historical Information:

In the MIPS I architecture, the LWL and LWR instructions were exceptions to the load-delay scheduling restriction.

A LWL or LWR instruction which was immediately followed by another LWL or LWR instruction, and used the same destination register would correctly merge the 1 to 4 loaded bytes with the data loaded by the previous instruction. All such restrictions were removed from the architecture in MIPS II.