Encoding:

COP0

010000

MFTR

01000

rt

rd

rx

u

h

0

sel

6

5

5

5

5

1

1

1

3

Format: 

MFTR rd, rt, u, sel, h

MIPS MT

Move from Thread Context

Purpose:

Move from Thread Context

To move the contents of a register within a targeted thread context or VPE into a general register of the current thread.

Description: 

GPR[rd] = TC[VPEControlTargTC][u,rt,sel,h]

The contents of the register specifieareloaded into general register rd. The target context to be read is determined by the value of the TargTC fiel of the CP0 VPEControl register (see Section 6.5). The register to be read within the selected context is determined by the value in the rt operand register, in conjunction with the u and sel bits of the MFTR instruction

Restrictions:

An MFTR instruction where the target TC is not in a Halted state (i.e., TCHalt.H is not set), or where a TC other than the one issuing the MFTR is active in the target VPE on a reference to a per-VPE CP0 register, may result in an

UNSTABLE value.

If the target TC is blocked but not halted,then the thread issuing the MFTR instrution may be blocked indefinitel.

Thisis dueto thetarget TC waiting on an externaleventthat may never happen.Itisrecommended thatthe

TCStatusRNST bit of the target TC be checked before issuing the MFTR instruction.

In any implementation with Floating-Point-Unit, if TCStatusTFR is set so the effective FPR width matches the GPR width, a MFTR instruction targetting one of the FPRs with h=1 will cause UNPREDICTABLE results.

Operation: 

if VPEConf0MVP = 0 and ( TC[VPEControlTargTC].TCBindCurVPE != TCBindCurVPE ) then
   data = -1
else if VPEControlTargTC > MVPConf0PTC then
   data = -1
else if u = 0 then
   data = TC[VPEControlTargTC].CPR[0,rt,sel]
else
if h = 1 then
      topbit = 63
      bottombit = 32
   else
      topbit = 31
      bottombit = 0
   endifcase sel
      0: data = TC[VPEControlTargTC].GPR[rt]
      1: case rt
         0: data = TC[VPEControlTargTC].Lo
         1: data = TC[VPEControlTargTC].Hi
         2: data = TC[VPEControlTargTC].ACX
         4: data = TC[VPEControlTargTC].DSPLo[1]
         5: data = TC[VPEControlTargTC].DSPHi[1]
         6: data = TC[VPEControlTargTC].DSPACX[1]
         8: data = TC[VPEControlTargTC].DSPLo[2]
         9: data = TC[VPEControlTargTC].DSPHI[2]
         10:data = TC[VPEControlTargTC].DSPACX[2]
         12 data = TC[VPEControlTargTC].DSPLo[3]
         13:data = TC[VPEControlTargTC].DSPHi[3]
         14:data = TC[VPEControlTargTC].DSPACX[3]
         16:data = TC[VPEControlTargTC].DSPControl
         otherwise: data = UNPREDICTABLE
         2: if ( ( ConfigAT = 0 and StatusFR = 0) or
                    ( ConfigAT = 1 or ConfigAT = 2) )
                   // GPR and FPR widths match
                   if (h = 0 )
                       data = TC[VPEControlTargTC].FPR[rt]
                   else
                       UNPREDICTABLE
                   endif
                elseif (ConfigAT = 0 and StatusFR = 1)
                   // 32-bit GPRs and 64-bit FPRs
                   data = TC[VPEControlTargTC].FPR[rt]topbit..bottombit
                endif
      3: data = TC[VPEControlTargTC].FPCR[rt]
      4: data = TC[VPEControlTargTC].CP2CPR[rx||rt]topbit..bottombit
      5: data = TC[VPEControlTargTC].CP2CCR[rx||rt]topbit..bottombit
      otherwise: data = UNPREDICTABLE
endif
if h = 1 then
   data = data63..32
endif
GPR[rd] = data31..0

Exceptions:

Coprocessor Unusable

Reserved Instruction