COP1X 010011 |
fr |
ft |
fs |
fd |
MADD 100 |
fmt |
6 |
5 |
5 |
5 |
5 |
3 |
3 |
MADD.fmt |
Floating Point Multiply Add | |
MADD.S fd, fr, fs, ft |
MIPS64, MIPS32 Release 2, removed in Release 6 |
Floating Point Multiply Add |
MADD.D fd, fr, fs, ft |
MIPS64, MIPS32 Release 2, removed in Release 6 |
Floating Point Multiply Add |
MADD.PS fd, fr, fs, ft |
MIPS64, MIPS32 Release 2, removed in Release 6 |
Floating Point Multiply Add |
Floating Point Multiply Add
To perform a combined multiply-then-add of FP values.
FPR[fd] = (FPR[fs] x FPR[ft]) + FPR[fr]
The value in FPR fs is multiplied by the value in FPR ft to produce an intermediate product.
The intermediate product is rounded according to the current rounding mode in FCSR. The value in FPR fr is added to the product. The result sum is calculated to infinite precision, rounded according to the current rounding mode in
FCSR, and placed into FPR fd. The operands and result are values in format fmt. The results and flags are as if separate floating-point multiply and add instructions were executed.
MADD.PS multiplies then adds the upper and lower halves of FPR fr, FPR fs, and FPR ft independently, and ORs together any generated exceptional conditions.
The Cause bits are ORed into the Flag bits if no exception is taken.
The fields fr, fs, ft, and fd must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is
UNPREDICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
The result of MADD.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model.
It is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
MADD.S and MADD.D: Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32
Release 1. Required in MIPS32 Release 2 and all subsequent versions of MIPS32. When required, these instructions are to be implemented if an FPU is present either in a 32-bit or 64-bit FPU or in a 32-bit or 64-bit FP Register Mode
(FIRF64=0 or 1, StatusFR=0 or 1).
This instruction has been removed in Release 6 and has been replaced by the fused multiply-add instruction. Refer to the fused multiply-add instruction 'MADDF.fmt' in this manual for more information. Release 6 does not support
Paired Single (PS).
vfr = ValueFPR(fr, fmt) vfs = ValueFPR(fs, fmt) vft = ValueFPR(ft, fmt) StoreFPR(fd, fmt, (vfs xfmt vft) +fmt vfr)
Coprocessor Unusable, Reserved Instruction
Inexact, Unimplemented Operation, Invalid Operation, Overflow, Underflow