Encoding:

Format:

MOD_U.df 

MOD_U.B wd,ws,wt

MOD_U.H wd,ws,wt

MOD_U.W wd,ws,wt

MOD_U.D wd,ws,wt

Purpose:

Vector Unsigned Modulo

Vector unsigned remainder (modulo).

Description:

wd[i] = ws[i] umod wt[i]

The unsigned integer elements in vector ws are divided by unsigned integer elements in vector wt. The remainder is written to vector wd. If a divisor element vector wt is zero, the result value is UNPREDICTABLE.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

MOD_U.B
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[ws]8i+7..8i umod WR[wt]8i+7..8i
   endfor
MOD_U.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i umod WR[wt]16i+15..16i
   endfor
MOD_U.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i umod WR[wt]32i+31..32i
   endfor
MOD_U.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i umod WR[wt]64i+63..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.