Encoding:

Format:

ASET bit, offset(base)

Purpose:

Atomically Set Bit within Byte

Description:

Disable interrupts;temp = memory[GPR[base] + offset]; temp = (temp or (1 <<bit)) ; memory[GPR[base] + offset] = temp; Enable Interrupts

The contents ofthe byte atthe memory location speciied by the effective address are fetched. The speciied bit within the byte is set to one. The modiied byte is stored in memory at the location speciied by the effective address.

The 12-bit signed offsetis added to the contents of GPR base to form the effective address. The read-modify-write sequence cannot be interrupted.

Transactions with locking semantics occurin some memory interconnects/busses.Itisimplementation-speciic whether this instruction uses such locking transactions.

Restrictions:

is UNPREDICTABLE if an ASET instruction is executed in the delay slot of aThe operation ofthe processor branch or jump instruction.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2)
TempIE = StatusIE
StatusIE = 0
memword = LoadMemory (CCA, BYTE, pAddr, vAddr, DATA)
byte = vAddr1..0 xor BigEndianCPU2
temp = memword7+8*byte..8*byte
temp = temp or ( 1 || 0bit)
dataword = temp || 08*byte
StoreMemory (CCA, BYTE, dataword, pAddr, vAddr, DATA)
StatusIE = TempIE

Exceptions:

TLB Reill, TLB Invalid, TLB Modiied, Address Error, Watch

Programming Notes:

Upon a TLB miss, a TLBS exception is signalled in the ExcCode ield ofthe Cause register. For address error, a

ADES exception is signalled in the ExcCode ield of the Cause register. For other data-stream related exceptions such as Debug Data Break exceptions and Watch exceptions, it is implementation-speciic whether this instruction is treated as a load or as a store.