Encoding:

SPECIAL3

011111

rs

0

00000

rd

RADDU.W.QB

10100

ADDU.QB

010000

6

5

5

5

5

6

Format: 

RADDU.W.QB rd, rs

MIPSDSP

Unsigned Reduction Add Vector Quad Bytes

Purpose:

Unsigned Reduction Add Vector Quad Bytes

Reduction add of four unsigned byte values in a vector register to produce an unsigned word result.

Description: 

rd = zero_extend(rs31..24 + rs23..16 + rs15..8 + rs7..0)

The four right-most unsigned byte elements in register rs are added together as unsigned 8-bit values, and the result is zero extended to a doubleword and written to register rd.

Restrictions:

No data-dependent exceptions are possible.

The operands must be in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

temp9..0 = ( 02 || GPR[rs]31..24 ) + ( 02 || GPR[rs]23..16 ) + ( 02 || GPR[rs]15..8 ) + ( 02 || GPR[rs]7..0 )
GPR[rd]63..0 = 0(GPRLEN-10) || temp9..0

Exceptions:

Reserved Instruction, DSP Disabled