NANOMIPS ISA Reference

MIPS_nanomips32_ISA_TRM_01_01_MD01247

ADD rd, rs, rt nanoMIPS, not available in NMS Add
ADDIU rt, rs, imm nanoMIPS, availability varies by format. Add Immediate (Untrapped)
ADDIUPC rt, imm nanoMIPS, availability varies by format. Add Immediate (Untrapped) to PC
ADDU dst, src1, src2 nanoMIPS, availability varies by format. Add (Untrapped)
ALIGN rd, rs, rt, bp Assembly alias Align
ALUIPC rt, %pcrel_hi(address) nanoMIPS Add aLigned Upper Immediate to PC
AND rd, rs, rt nanoMIPS AND
ANDI rt, rs, u nanoMIPS AND Immediate
BALC address nanoMIPS Branch And Link, Compact
BALRSC rt, rs nanoMIPS Branch And Link Register Scaled, Compact
BBEQZC rt, bit, address nanoMIPS, not available in NMS Branch if Bit Equals Zero, Compact
BBNEZC rt, bit, address nanoMIPS, not available in NMS Branch if Bit Not Equal to Zero, Compact
BC address nanoMIPS Branch, Compact
BEQC rs, rt, address nanoMIPS, availability varies by format. Branch if Equal, Compact
BEQIC rt, u, address nanoMIPS Branch if Equal to Immediate, Compact
BEQZC rt, address # when rt andaddressarein range nanoMIPS Branch if Equal to Zero, Compact
BGEC rs, rt, address nanoMIPS Branch if Greater than or Equal, Compact
BGEIC rt, u, address nanoMIPS Branch if Greater than or Equal to Immediate, Compact
BGEIUC rt, u, address nanoMIPS Branch if Greater than or Equal to Immediate Unsigned, Compact
BGEUC rs, rt, address nanoMIPS Branch if Greater than or Equal
BITREVB rt, rs Assembly alias, not available in NMS Bit Reverse in Bytes
BITREVH rt, rs Assembly alias, not available in NMS Bit Reverse in Halfs
BITREVW rt, rs Assembly alias, not available in NMS Bit Reverse in Word
BITSWAP rt, rs Assembly alias, not available in NMS Bitswap
BLTC rs, rt, address nanoMIPS Branch if Less Than, Compact
BLTIC rt, u, address nanoMIPS Branch if Less Than Immediate, Compact
BLTIUC rt, u, address nanoMIPS Branch if Less Than Immediate Unsigned Compact
BLTUC rs, rt, address nanoMIPS Branch if Less Than Unsigned, Compact
BNEC rs, rt, address nanoMIPS, availability varies by format. Branch Not Equal, Compact
BNEIC rt, u, address nanoMIPS Branch if Not Equal to Immediate, Compact
BNEZC rt, address nanoMIPS Branch if Not Equal to Zero, Compact
BREAK code nanoMIPS Break
BRSC rs nanoMIPS Branch Register Scaled, Compact
BYTEREVH rt, rs Assembly alias, not available in NMS Byte Reverse in Halfs
BYTEREVW rt, rs Assembly alias, not available in NMS Byte Reverse in Word
CACHE op, offset(rs) nanoMIPS. Requires CP0 privilege, availability varies by format. Cache operation/Cache operation using EVA addressing
CACHEE op, offset(rs) nanoMIPS. Requires CP0 privilege, availability varies by format. Cache operation/Cache operation using EVA addressing
CLO rt, rs nanoMIPS, not available in NMS Count Leading Ones
CLZ rt, rs nanoMIPS, not available in NMS Count Leading Zeros
CRC32B rt, rs nanoMIPS. Optional, present when Config5.CRCP=1. CRC32 Byte.
CRC32CB rt, rs nanoMIPS. Optional, present when Config5.CRCP=1. CRC32 (Castagnoli) Byte
CRC32CH rt, rs nanoMIPS. Optional, present when Config5.CRCP=1. CRC32 (Castagnoli) Half
CRC32CW rt, rs nanoMIPS. Optional, present when Config5.CRCP=1. CRC32 (Castagnoli) Word
CRC32H rt, rs nanoMIPS. Optional, present when Config5.CRCP=1. CRC32 Half.
CRC32W rt, rs nanoMIPS. Optional, present when Config5.CRCP=1. CRC32 Word.
DERET nanoMIPS. Optional, present when Debug implemented. Debug Exception Return
DI rt nanoMIPS. Requires CP0 privilege. Disable Interrupts
DIV rd, rs, rt nanoMIPS Divide
DIVU rd, rs, rt nanoMIPS Divide Unsigned
DVP rt nanoMIPS. Optional, present when Config5.VP=1, otherwise NOP. Requires CP0 privilege. Disable Virtual Processors
EHB nanoMIPS Execution hazard barrier
EI rt nanoMIPS. Requires CP0 privilege. Enable Interrupts
ERET nanoMIPS, availability varies by format. Exception Return/Exception Return Not Clearing LLBit
ERETNC nanoMIPS, availability varies by format. Exception Return/Exception Return Not Clearing LLBit
EVP rt nanoMIPS. Optional, present when Config5.VP=1, otherwise NOP. Requires CP0 privilege. Enable Virtual
EXT rt, rs, pos, size nanoMIPS, not available in NMS Extract
EXTW rd, rs, rt, shift nanoMIPS Extract Word
GINVI rs nanoMIPS. Optional, present when Globally Invalidate Instruction caches
GINVT rs, type nanoMIPS. Optional, present when Config5.GI=3. Requires CP0 privilege. Globally invalidate TLBs
INS rt, rs, pos, size nanoMIPS, not available in NMS Insert. Merge a right justified bit field of size size from register $rs into position pos of
JALRC.HB rt, rs nanoMIPS Jump And Link Register, Compact, with Hazard Barrier. Unconditional
JALRC dst, src nanoMIPS Jump And Link Register, Compact. Unconditional
JRC rt nanoMIPS Jump Register, Compact. Unconditional jump to address in register $rt.
LAPC rt, address Assembly alias. NMS cores restricted to 21 bit signed offset from PC. Load Address, PC relative
LB rt, offset(rs) nanoMIPS Load Byte
LBE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Load Byte using EVA addressing
LBU rt, offset(rs) nanoMIPS Load Byte Unsigned
LBUE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Load Byte Unsigned using EVA addressing
LBUX rd, rs(rt) nanoMIPS Load Byte Unsigned indeXed
LBX rd, rs(rt) nanoMIPS Load Byte indeXed
LH rt, offset(rs) nanoMIPS Load Half
LHE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Load Half using EVA addressing
LHU rt, offset(rs) nanoMIPS Load Half Unsigned
LHUE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Load Half Unsigned using EVA addressing
LHUX rd, rs(rt) nanoMIPS Load Half Unsigned indeXed
LHUXS rd, rs(rt) nanoMIPS Load Half Unsigned indeXed Scaled
LHX rd, rs(rt) nanoMIPS Load Half indeXed
LHXS rd, rs(rt) nanoMIPS Load Half indeXed Scaled
LI rt, s nanoMIPS, availability varies by format. Load Immediate
LL rt, offset(rs) nanoMIPS, availability varies by format. Load Linked word/Load Linked word using EVA addressing/Load Linked Word Pair/Load
LLE rt, offset(rs) nanoMIPS, availability varies by format. Load Linked word/Load Linked word using EVA addressing/Load Linked Word Pair/Load
LLWP rt, ru, (rs) nanoMIPS, availability varies by format. Load Linked word/Load Linked word using EVA addressing/Load Linked Word Pair/Load
LLWPE rt, ru, (rs) nanoMIPS, availability varies by format. Load Linked word/Load Linked word using EVA addressing/Load Linked Word Pair/Load
LSA rd, rs, rt, u2 nanoMIPS Load Scaled Address
LUI rt, %hi(imm) nanoMIPS Load Upper Immediate.
LW rt, offset(rs) nanoMIPS, availability varies by format. Load Word
LWE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Load Word using EVA addressing
LWM rt, offset(rs), count nanoMIPS, not available in NMS Load Word Multiple
LWPC rt, address nanoMIPS, not available in NMS Load Word PC relative
LWX rd, rs(rt) nanoMIPS Load Word indeXed
LWXS rd, rs(rt) nanoMIPS Load Word indeXed Scaled
MFC0 rt, c0s, sel nanoMIPS. Requires CP0 privilege. Move From Coprocessor 0
MFHC0 rt, c0s, sel nanoMIPS, required. Move From High Coprocessor 0
MOD rd, rs, rt nanoMIPS Modulo
MODU rd, rs, rt nanoMIPS Modulo Unsigned
MOVE.BALC rd, rt, address nanoMIPS, not available in NMS Move and Branch and Link, Compact
MOVE rt, rs nanoMIPS Move
MOVEP dst1, dst2, src1, src2 nanoMIPS, not available in NMS Move Pair
MOVN rd, rs, rt nanoMIPS Move if Not zero
MOVZ rd, rs, rt nanoMIPS Move if Zero
MTC0 rt, c0s, sel nanoMIPS. Requires CP0 privilege. Move To Coprocessor 0
MTHC0 rt, c0s, sel nanoMIPS, required. Move To High Coprocessor 0
MUH rd, rs, rt nanoMIPS Multiply High
MUHU rd, rs, rt nanoMIPS Multiply High Unsigned
MUL dst, src1, src2 nanoMIPS, availability varies by format. Multiply
MULU rd, rs, rt nanoMIPS Multiply Unsigned
NOP nanoMIPS No Operation
NOR rd, rs, rt nanoMIPS NOR
NOT rt, rs nanoMIPS NOT
OR rd, rs, rt nanoMIPS OR
ORI rt, rs, u nanoMIPS OR Immediate
PAUSE nanoMIPS Pause
PREF hint, offset(rs) nanoMIPS, availability varies by format. Prefetch/Prefetch using EVA addressing
PREFE hint, offset(rs) nanoMIPS, availability varies by format. Prefetch/Prefetch using EVA addressing
RDHWR rt, hs, sel nanoMIPS, not available in NMS Read Hardware Register
RDPGPR rt, rs nanoMIPS. Requires CP0 privilege. Read Previous GPR
RESTORE u[, dst1 [, dst2 [, ...]]] # jr=0 implied nanoMIPS, availability varies by format. Restore callee saved registers/Restore callee saved registers and Jump to Return address,
RESTORE.JRC u[, dst1 [, dst2 [, ...]]] # jr=1 implied nanoMIPS, availability varies by format. Restore callee saved registers/Restore callee saved registers and Jump to Return address,
ROTR rt, rs, shift nanoMIPS Rotate Right
ROTRV rd, rs, rt nanoMIPS Rotate Right Variable
ROTX rt, rs, shift, shiftx, stripe nanoMIPS, not available in NMS Rotate and eXchange
SAVE u[, src1 [, src2 [, ...]]] nanoMIPS, availability varies by format. Save callee saved registers
SB rt, offset(rs) nanoMIPS Store Byte
SBE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Store Byte using EVA addressing
SBX rd, rs(rt) nanoMIPS, not available in NMS Store Byte indeXed
SC rt, offset(rs) nanoMIPS, availability varies by format. Store Conditional word/Store Conditional word using EVA addressing/Store Conditional
SCE rt, offset(rs) nanoMIPS, availability varies by format. Store Conditional word/Store Conditional word using EVA addressing/Store Conditional
SCWP rt, ru, (rs) nanoMIPS, availability varies by format. Store Conditional word/Store Conditional word using EVA addressing/Store Conditional
SCWPE rt, ru, (rs) nanoMIPS, availability varies by format. Store Conditional word/Store Conditional word using EVA addressing/Store Conditional
SDBBP code nanoMIPS. Optional, present when Debug implemented. Software Debug Breakpoint
SEB rt, rs nanoMIPS, not available in NMS Sign Extend Byte
SEH rt, rs nanoMIPS Sign Extend Half
SEQI rt, rs, u nanoMIPS Set on Equal to Immediate
SH rt, offset(rs) nanoMIPS Store Half
SHE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Store Half using EVA addressing
SHX rd, rs(rt) nanoMIPS, not available in NMS Store Half indeXed
SHXS rd, rs(rt) nanoMIPS, not available in NMS Store Half
SIGRIE code nanoMIPS Signal Reserved Instruction Exception
SLL rt, rs, shift nanoMIPS Shift Left Logical
SLLV rd, rs, rt nanoMIPS Shift Left Logical Variable
SLT rd, rs, rt nanoMIPS Set on Less Than
SLTI rt, rs, u nanoMIPS Set on Less Than Immediate
SLTIU rt, rs, u nanoMIPS Set on Less Than Immediate, Unsigned
SLTU rd, rs, rt nanoMIPS Set on Less Than, Unsigned
SOV rd, rs, rt nanoMIPS Set on Overflow
SRA rt, rs, shift nanoMIPS Shift Right Arithmetic
SRAV rd, rs, rt nanoMIPS Shift Right Arithmetic Variable
SRL rt, rs, shift nanoMIPS Shift Right Logical.
SRLV rd, rs, rt nanoMIPS Shift Right Logical Variable
SUB rd, rs, rt nanoMIPS, not available in NMS Subtract
SUBU rd, rs, rt nanoMIPS Subtract (Untrapped)
SW rt, offset(rs) nanoMIPS, availability varies by format. Store Word
SWE rt, offset(rs) nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege. Store Word using EVA addressing
SWM rt, offset(rs), count nanoMIPS, not available in NMS Store Word Multiple.
SWPC rt, address nanoMIPS, not available in NMS Store Word PC relative
SWX rd, rs(rt) nanoMIPS, not available in NMS Store Word indeXed
SWXS rd, rs(rt) nanoMIPS, not available in NMS Store Word indeXed Scaled
SYNC stype nanoMIPS Sync
SYNCI offset(rs) nanoMIPS, availability varies by format. SYNChronize Instruction cache/SYNChronize Instruction cache using EVA addressing
SYNCIE offset(rs) nanoMIPS, availability varies by format. SYNChronize Instruction cache/SYNChronize Instruction cache using EVA addressing
SYSCALL code nanoMIPS System Call
TEQ rs, rt, code nanoMIPS, not available in NMS Trap if Equal
TLBINV nanoMIPS. Required on TLB cores, unless Config5.IE<2. Requires CP0 privilege. TLB Invalidate
TLBINVF nanoMIPS. Required on TLB cores, unless Config5.IE<2. Requires CP0 privilege. TLB Invalidate Flush
TLBP nanoMIPS. Required on TLB cores. Requires CP0 privilege. TLB Probe
TLBR nanoMIPS. Required on TLB cores. Requires CP0 privilege. TLB Read
TLBWI nanoMIPS. Required on TLB cores. Requires CP0 privilege. TLB Write Indexed
TLBWR nanoMIPS. Required on TLB cores. Requires CP0 privilege. TLB Write Random
TNE rs, rt, code nanoMIPS, not available in NMS Trap if Not Equal
UALH rt, offset(rs) nanoMIPS, not available in NMS Unaligned Load Half
UALW rt, offset(rs) Assembly alias, not available in NMS Unaligned Load Word
UALWM rt, offset(rs), count nanoMIPS, not available in NMS Unaligned Load Word Multiple
UASH rt, offset(rs) nanoMIPS, not available in NMS Unaligned Store Half
UASW rt, offset(rs) Assembly alias, not available in NMS Unaligned Store Word
UASWM rt, offset(rs), count nanoMIPS, not available in NMS Unaligned Store Word Multiple
WAIT code nanoMIPS Wait
WRPGPR rt, rs nanoMIPS. Requires CP0 privilege. Write Previous GPR
WSBH rt, rs Assembly alias, not available in NMS Word Swap Byte Half
XOR rd, rs, rt nanoMIPS XOR
XORI rt, rs, u nanoMIPS XOR Immediate

NANOMIPS ASE-DSP ISA Reference

MIPS_nanoMIPS32_DSP_00_04_MD01249

ABSQ_S.PH rt, rs DSP Find Absolute Value of Two Fractional Halfwords
ABSQ_S.QB rt, rs DSP-R2 Find Absolute Value of Four Fractional Byte Values
ABSQ_S.W rt, rs DSP Find Absolute Value of Fractional Word
ADDQH.PH rd, rs, rt DSP-R2 Add Fractional Halfword Vectors And Shift Right to Halve Results
ADDQH_R.PH rd, rs, rt DSP-R2 Add Fractional Halfword Vectors And Shift Right to Halve Results
ADDQH.W rd, rs, rt DSP-R2 Add Fractional Words And Shift Right to Halve Results
ADDQH_R.W rd, rs, rt DSP-R2 Add Fractional Words And Shift Right to Halve Results
ADDQ.PH rd, rs, rt DSP Add Fractional Halfword Vectors
ADDQ_S.PH rd, rs, rt DSP Add Fractional Halfword Vectors
ADDQ_S.W rd, rs, rt DSP Add Fractional Words
ADDSC rd, rs, rt DSP Add Signed Word and Set Carry Bit
ADDUH.QB rd, rs, rt DSP-R2 Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results
ADDUH_R.QB rd, rs, rt DSP-R2 Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results
ADDU.PH rd, rs, rt DSP-R2 Unsigned Add Integer Halfwords
ADDU_S.PH rd, rs, rt DSP-R2 Unsigned Add Integer Halfwords
ADDU.QB rd, rs, rt DSP Unsigned Add Quad Byte Vectors
ADDU_S.QB rd, rs, rt DSP Unsigned Add Quad Byte Vectors
ADDWC rd, rs, rt DSP Add Word with Carry Bit
BALIGN rt, rs, bp DSP-R2 Byte Align Contents from Two Registers
EXTW rt, rs, rt, 8*(4-bp) Replaced with EXTW in nanoMIPS Byte Align Contents from Two Registers
BITREV rt, rs DSP Bit-Reverse Halfword
BPOSGE32C offset DSP-R3 Branch on Greater Than or Equal To Value 32 in
CMP.EQ.PH rs, rt DSP Compare Vectors of Signed Integer Halfword Values
CMP.LT.PH rs, rt DSP Compare Vectors of Signed Integer Halfword Values
CMP.LE.PH rs, rt DSP Compare Vectors of Signed Integer Halfword Values
CMPGU.EQ.QB rd, rs, rt DSP Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPGU.LT.QB rd, rs, rt DSP Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPGU.LE.QB rd, rs, rt DSP Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPU.EQ.QB rs, rt DSP Compare Vectors of Unsigned Byte Values
CMPU.LT.QB rs, rt DSP Compare Vectors of Unsigned Byte Values
CMPU.LE.QB rs, rt DSP Compare Vectors of Unsigned Byte Values
DPA.W.PH ac, rs, rt DSP-R2 Dot Product with Accumulate on Vector Integer Halfword Elements
DPAQX_S.W.PH ac, rs, rt DSP-R2 Cross Dot Product with Accumulation on Fractional Halfword Elements
DPAQX_SA.W.PH ac, rs, rt DSP-R2 Cross Dot Product with Accumulation on Fractional Halfword Elements
DPAQ_S.W.PH ac, rs, rt DSP Dot Product with Accumulation on Fractional Halfword Elements
DPAQ_SA.L.W ac, rs, rt DSP Dot Product with Accumulate on Fractional Word Element
DPAU.H.QBL ac, rs, rt DSP Dot Product with Accumulate on Vector Unsigned Byte Elements
DPAU.H.QBR ac, rs, rt DSP Dot Product with Accumulate on Vector Unsigned Byte Elements
DPAX.W.PH ac, rs, rt DSP-R2 Cross Dot Product with Accumulate on Vector Integer Halfword Elements
DPS.W.PH ac, rs, rt DSP-R2 Dot Product with Subtract on Vector Integer Half-Word Elements
DPSQX_S.W.PH ac, rs, rt DSP-R2 Cross Dot Product with Subtraction on Fractional Halfword Elements
DPSQX_SA.W.PH ac, rs, rt DSP-R2 Cross Dot Product with Subtraction on Fractional Halfword Elements
DPSQ_S.W.PH ac, rs, rt DSP Dot Product with Subtraction on Fractional Halfword Elements
DPSQ_SA.L.W ac, rs, rt DSP Dot Product with Subtraction on Fractional Word Element
DPSU.H.QBL ac, rs, rt DSP Dot Product with Subtraction on Vector Unsigned Byte Elements
DPSU.H.QBR ac, rs, rt DSP Dot Product with Subtraction on Vector Unsigned Byte Elements
DPSX.W.PH ac, rs, rt DSP-R2 Cross Dot Product with Subtract on Vector Integer Halfword Elements
EXTPDP rt, ac, size DSP Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos
EXTP rt, ac, size DSP Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR
EXTPV rt, ac, rs DSP Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR
EXTRV.W rt, ac, rs DSP Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_R.W rt, ac, rs DSP Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_RS.W rt, ac, rs DSP Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_S.H rt, ac, rs DSP Extract Halfword Value Variable From Accumulator to GPR With Right Shift and Saturate
EXTR.W rt, ac, shift DSP Extract Word Value With Right Shift From Accumulator to GPR
EXTR_R.W rt, ac, shift DSP Extract Word Value With Right Shift From Accumulator to GPR
EXTR_RS.W rt, ac, shift DSP Extract Word Value With Right Shift From Accumulator to GPR
EXTR_S.H rt, ac, shift DSP Extract Halfword Value From Accumulator to GPR With Right Shift and Saturate
INSV rt, rs MIPSDSP Insert Bit Field Variable
LBUX rd, index(base) DSP Load Unsigned Byte Indexed
LBUX rd, rs(rt) Replaced with LBUX in nanoMIPS Load Unsigned Byte Indexed
LHX rd, index(base) DSP Load Halfword Indexed
LHX rd, rs(rt) Replaced with LHX in nanoMIPS Load Halfword Indexed
LWX rd, index(base) DSP Load Word Indexed
LWX rd, rs(rt) Replaced with LWX in nanoMIPS Load Word Indexed
MADD ac, rs, rt DSP Multiply Word and Add to Accumulator
MADDU ac, rs, rt DSP Multiply Unsigned Word and Add to Accumulator
MAQ_S.W.PHL ac, rs, rt DSP Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_SA.W.PHL ac, rs, rt DSP Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_S.W.PHR ac, rs, rt DSP Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_SA.W.PHR ac, rs, rt DSP Multiply with Accumulate Single Vector Fractional Halfword Element
MFHI rs, ac DSP Move from HI register
MFLO rt, ac DSP Move from LO register
MODSUB rd, rs, rt DSP Modular Subtraction on an Index Value
MSUB ac, rs, rt DSP Multiply Word and Subtract from Accumulator
MSUBU ac, rs, rt DSP Multiply Unsigned Word and Add to Accumulator
MTHI rs, ac DSP Move to HI register
MTHLIP rs, ac DSP Copy LO to HI and a GPR to LO and Increment Pos by 32
MTLO rs, ac DSP Move to LO register
MULEQ_S.W.PHL rd, rs, rt DSP Multiply Vector Fractional Left Halfwords to Expanded Width Products
MULEQ_S.W.PHR rd, rs, rt DSP Multiply Vector Fractional Right Halfwords to Expanded Width Products
MULEU_S.PH.QBL rd, rs, rt DSP Multiply Unsigned Vector Left Bytes by Halfwords to Halfword Products
MULEU_S.PH.QBR rd, rs, rt DSP Multiply Unsigned Vector Right Bytes with halfwords to Half Word Products
MULQ_RS.PH rd, rs, rt DSP Multiply Vector Fractional Halfwords to Fractional Halfword Products
MULQ_RS.W rd, rs, rt DSP-R2 Multiply Fractional Words to Same Size Product with Saturation and Rounding
MULQ_S.PH rd, rs, rt DSP-R2 Multiply Vector Fractional Half-Words to Same Size Products
MULQ_S.W rd, rs, rt DSP-R2 Multiply Fractional Words to Same Size Product with Saturation
MULSA.W.PH ac, rs, rt DSP-R2 Multiply and Subtract Vector Integer Halfword Elements and Accumulate
MULSAQ_S.W.PH ac, rs, rt DSP Multiply And Subtract Vector Fractional Halfwords And Accumulate
MULT ac, rs, rt DSP Multiply Word
MULTU ac, rs, rt DSP Multiply Unsigned Word
MUL.PH rd, rs, rt DSP-R2 Multiply Vector Integer HalfWords to Same Size Products
MUL_S.PH rd, rs, rt DSP-R2 Multiply Vector Integer HalfWords to Same Size Products
PACKRL.PH rd, rs, rt DSP Pack a Vector of Halfwords from Vector Halfword Sources
PICK.PH rd, rs, rt DSP Pick a Vector of Halfword Values Based on Condition Code Bits
PICK.QB rd, rs, rt DSP Pick a Vector of Byte Values Based on Condition Code Bits
PRECEQ.W.PHL rt, rs DSP Precision Expand Fractional Halfword to Fractional Word Value
PRECEQ.W.PHR rt, rs DSP Precision Expand Fractional Halfword to Fractional Word Value
PRECEQU.PH.QBLA rt, rs DSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBL rt, rs DSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBRA rt, rs DSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBR rt, rs DSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEU.PH.QBLA rt, rs DSP Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBL rt, rs DSP Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBRA rt, rs DSP Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBR rt, rs DSP Precision Expand two Unsigned Bytes to Unsigned Halfword Values
PRECR.QB.PH rd, rs, rt DSP-R2 Precision Reduce Four Integer Halfwords to Four Bytes
PRECRQ.PH.W rd, rs, rt DSP Precision Reduce Fractional Words to Fractional Halfwords
PRECRQ.QB.PH rd, rs, rt DSP Precision Reduce Four Fractional Halfwords to Four Bytes
PRECRQU_S.QB.PH rd, rs, rt DSP Precision Reduce Fractional Halfwords to Unsigned Bytes With Saturation
PRECRQ_RS.PH.W rd, rs, rt DSP Precision Reduce Fractional Words to Halfwords With Rounding and Saturation
PRECR_SRA.PH.W rt, rs, sa DSP-R2 Precision Reduce Two Integer Words to Halfwords after a Right Shift
PRECR_SRA_R.PH.W rt, rs, sa DSP-R2 Precision Reduce Two Integer Words to Halfwords after a Right Shift
PREPEND rt, rs, sa DSP-R2 Right Shift and Prepend Bits to the MSB
EXTW rt, rs, rt, sa Replaced with EXTW in nanoMIPS Right Shift and Prepend Bits to the MSB
RADDU.W.QB rt, rs DSP Unsigned Reduction Add Vector Quad Bytes
RDDSP rt, mask DSP Read DSPControl Register Fields to a GPR
REPL.PH rd, immediate DSP Replicate Immediate Integer into all Vector Element Positions
REPL.QB rt, immediate DSP Replicate Immediate Integer into all Vector Element Positions
REPLV.PH rt, rs DSP Replicate a Halfword into all Vector Element Positions
REPLV.QB rt, rs DSP Replicate Byte into all Vector Element Positions
SHILO ac, shift DSP Shift an Accumulator Value Leaving the Result in the Same Accumulator
SHILOV ac, rs DSP Variable Shift of Accumulator Value Leaving the Result in the Same Accumulator
SHLL.QB rt, rs, sa DSP Shift Left Logical Vector Quad Bytes
SHLLV.QB rd, rt, rs DSP Shift Left Logical Variable Vector Quad Bytes
SHLLV.PH rd, rt, rs DSP Shift Left Logical Variable Vector Pair Halfwords
SHLLV_S.PH rd, rt, rs DSP Shift Left Logical Variable Vector Pair Halfwords
SHLLV_S.W rd, rt, rs DSP Shift Left Logical Variable Vector Word
SHLL.PH rt, rs, sa DSP Shift Left Logical Vector Pair Halfwords
SHLL_S.PH rt, rs, sa DSP Shift Left Logical Vector Pair Halfwords
SHLL_S.W rt, rs, sa DSP Shift Left Logical Word with Saturation
SHRAV.PH rd, rt, rs DSP Shift Right Arithmetic Variable Vector Pair Halfwords
SHRAV_R.PH rd, rt, rs DSP Shift Right Arithmetic Variable Vector Pair Halfwords
SHRAV.QB rd, rt, rs DSP-R2 Shift Right Arithmetic Variable Vector of Four Bytes
SHRAV_R.QB rd, rt, rs DSP-R2 Shift Right Arithmetic Variable Vector of Four Bytes
SHRAV_R.W rd, rt, rs DSP Shift Right Arithmetic Variable Word with Rounding
SHRA.PH rt, rs, sa DSP Shift Right Arithmetic Vector Pair Halfwords
SHRA_R.PH rt, rs, sa DSP Shift Right Arithmetic Vector Pair Halfwords
SHRA.QB rt, rs, sa DSP-R2 Shift Right Arithmetic Vector of Four Bytes
SHRA_R.QB rt, rs, sa DSP-R2 Shift Right Arithmetic Vector of Four Bytes
SHRA_R.W rt, rs, sa DSP Shift Right Arithmetic Word with Rounding
SHRL.PH rt, rs, sa DSP-R2 Shift Right Logical Two Halfwords
SHRL.QB rt, rs, sa DSP Shift Right Logical Vector Quad Bytes
SHRLV.PH rd, rt, rs DSP-R2 Shift Variable Right Logical Pair of Halfwords
SHRLV.QB rd, rt, rs DSP Shift Right Logical Variable Vector Quad Bytes
SUBQH.PH rd, rs, rt DSP-R2 Subtract Fractional Halfword Vectors And Shift Right to Halve Results
SUBQH_R.PH rd, rs, rt DSP-R2 Subtract Fractional Halfword Vectors And Shift Right to Halve Results
SUBQH.W rd, rs, rt DSP-R2 Subtract Fractional Words And Shift Right to Halve Results
SUBQH_R.W rd, rs, rt DSP-R2 Subtract Fractional Words And Shift Right to Halve Results
SUBQ.PH rd, rs, rt DSP Subtract Fractional Halfword Vector
SUBQ_S.PH rd, rs, rt DSP Subtract Fractional Halfword Vector
SUBQ_S.W rd, rs, rt DSP Subtract Fractional Word
SUBUH.QB rd, rs, rt DSP-R2 Subtract Unsigned Bytes And Right Shift to Halve Results
SUBUH_R.QB rd, rs, rt DSP-R2 Subtract Unsigned Bytes And Right Shift to Halve Results
SUBU.PH rd, rs, rt DSP-R2 Subtract Unsigned Integer Halfwords
SUBU_S.PH rd, rs, rt DSP-R2 Subtract Unsigned Integer Halfwords
SUBU.QB rd, rs, rt DSP Subtract Unsigned Quad Byte Vector
SUBU_S.QB rd, rs, rt DSP Subtract Unsigned Quad Byte Vector
WRDSP rt, mask DSP Write Fields to DSPControl Register from a GPR

NANOMIPS ASE-MT ISA Reference

MIPS_nanoMIPS32_MT_TRM_01_17_MD01255

DMT rt MIPS MT Disable Multi-Threaded Execution
DVPE rt MIPS MT Disable Virtual Processor Execution
EMT rt MIPS MT Enable Multi-Threaded Execution
EVPE rt MIPS MT Enable Virtual Processor Execution
FORK rd, rs, rt MIPS MT Allocate and Schedule a New Thread
MFTR rt, rs, u, sel, h MIPS MT Move from Thread Context
MTTR rt, rs, u, sel, h MIPS MT Move to Thread Context
YIELD rt, rs MIPS MT Conditionally Deschedule or Deallocate the Current Thread