Assembly:

EHB

Purpose:

Execution hazard barrier. Clear all execution hazards before allowing any subsequent instructions to graduate.

Availability:

nanoMIPS

Format:

Operation:

clear_execution_hazards()

The EHB instruction creates an execution hazard barrier, meaning thatit ensures that subsequent

instructions will be aware of changes to CP0 state caused by prior instructions. Examples of instructions which change CP0 state and which need an execution hazard barrier to ensure that subsequent

instructions see those updates are MTC0, EI, DI, TLBR and CACHE/CACHEE

In the absence of an execution hazard barrier, the CP0 register value used as input to an instruction may be out of date, since it may have been read before the write to the CP0 register by a prior instruction

has actually been committed.

An execution hazard barrier is sufficient to ensure that a fetched instruction is aware of all prior CP0 updates. However, it is not sufficient to ensure that the correct instruction is being fetched as a result

of those CP0 updates. Ensuring that the correct instruction is fetched requires an instruction hazard barrier, which is provided by the JALRC.HB instruction, or any ofthe exception return instructions

ERET/ERETNC or DERET.

Exceptions:

None.