ERET - Exception Return/Exception Return Not Clearing LLBit

Assembly:

ERET	nanoMIPS, availability varies by format.	Exception Return/Exception Return Not Clearing LLBit
ERETNC	nanoMIPS, availability varies by format.	Exception Return/Exception Return Not Clearing LLBit

Purpose:

Exception Return/Exception Return Not Clearing LLBit. Return from an exception: either byclearing Status.ERL if set and jumping to the address in ErrorEPC; otherwise by clearing Status.EXL,

jumping to the address in EPC, and updating the current Shadow Register Setto SRSCtl.PSS if required.

Availability:

nanoMIPS, availability varies by format.

Format:

ERET, requires CP0 privilege.

001000	x	0	11	11001	101	111	111
6	9	1	2	5	3	3	3

nc = False

ERETNC, present when Config5.LLB=1. Requires CP0 privilege.

001000	x	1	11	11001	101	111	111
6	9	1	2	5	3	3	3

nc = True

Operation:

if nc and C0.Config5.LLB == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if C0.Status.ERL == 1:
    effective_epc = sign_extend(C0.ErrorEPC)
    C0.Status.ERL = 0
else:
    effective_epc = sign_extend(C0.EPC)
    C0.Status.EXL = 0
    if C0.SRSCtl.HSS > 0 and C0.Status.BEV == 0:
        C0.SRSCtl.CSS = C0.SRSCtl.PSS
CPU.next_pc = effective_epc
# clear LLbit unless this is an ERETNC
if not nc:
   C0.LLAddr.LLB = 0
clear_execution_hazards()
clear_instruction_hazards()

The ERET/ERETNC instructions implement a software barrier that resolves all execution and instruction hazards. See the EHB and JALRC.HB instructions for an explanation of execution and instruction

hazards respectively, and also the SYNCI/SYNCIE instruction for additionalinformation on resolving instruction hazards created by writing to the instruction stream.

The eﬀects of the ERET/ERETNC barrier are seen starting with the fetch and decode of the instruction at the PC to which the ERET returns. This means, for instance, that if C0.EPC is modiﬁed by an MTC0

instruction prior to an ERET, an EHB is required between the MTC0 and the ERET to ensure that the ERET uses the correct EPC value.

Conﬁg5.LLB indicates support for the ERETNC instruction.It is always 1 for R6 cores, except for those implementing the nanoMIPS™ subset.In other words, ERETNC is required for nanoMIPS™ cores and

optional for NMS cores.

Exceptions:

Coprocessor Unusable. Reserved Instruction allowed for ERETNC on NMS cores.