Encoding:

P32A

001000

rt

rs

0111000

100

111

111

6

5

5

7

3

3

3

Format: 

PRECEQU.PH.QBL rt, rs

DSP

Precision Expand two Unsigned Bytes to Fractional Halfword Values

Purpose:

Precision Expand two Unsigned Bytes to Fractional Halfword Values

Expand the precision of two unsigned byte values taken from the two left-most elements of a quad byte vector to create two Q15 fractional halfword values.

Description: 

rt = expand_prec(rs31..24) || expand_prec(rs23..16)

The two left-most unsigned integer byte values from the four byte elements in register rs are expanded to create two

Q15 fractional values that are then written to destination register rt. The precision expansion is achieved by pre-pending a single zero bit (for positive sign) to the original byte value and appending seven least-significant zeros to generate each 16-bit fractional value.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

ValidateAccessToDSPResources()
tempB15..0 = 01 || GPR[rs]31..24 || 07 
tempA15..0 = 01 || GPR[rs]23..16 || 07 
GPR[rt]31..0 = tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled