Assembly:

JALRC.HB rt, rs

Purpose:

Jump And Link Register, Compact, with Hazard Barrier. Unconditionaljump to address in

register $rs, placing the return address in register $rt. Clear allinstruction and execution hazards before allowing any subsequent instructions to graduate.

Availability:

nanoMIPS

Format:

Operation:

address = GPR[rs] + 0
GPR[rt] = CPU.next_pc
CPU.next_pc = address
clear_instruction_hazards()
clear_execution_hazards()

The JALRC.HB instruction creates an instruction hazard barrier, meaning that it ensures that subsequent

instruction fetches will be aware of state changes caused by prior instructions.Examples of

state changes which affect instruction fetch and which need an instruction hazard barrier to ensure that subsequent instructions see those updates are:

• Writes to the instruction stream (which must also have been synchronized by a SYNCI/SYNCIE

and a SYNC).

• Updates to the TLB.

• Changes in CP0 state which affect addresses mappings.

In the absence of an instruction hazard barrier, the state used as input to an instruction fetch may be out of date, since it may have been read before the updates to that state have actually completed.

JALRC.HB also provides an execution hazard barrier, see the EHB instruction definition for details. An instruction hazard barrier is also provided by any of the exception return instructions ERET/ERETNC,

or DERET, but those instructions are only available to privileged software, whereas JALRC.HB is available from all operating modes.

Exceptions:

None.