Assembly:

UASH rt, offset(rs)

Purpose:

Unaligned Store Half. Store halfword from register $rt to memory address $rs + offset(register plus immediate), guaranteeing that the operation completes even if the address is not halfword aligned.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
offset = sign_extend(s, from_nbits=9)
va = effective_address(GPR[rs], offset, 'Store')
data = zero_extend(GPR[rt], from_nbits=16)
write_memory_at_va(data, va, nbytes=2, unaligned_support='always')

UASH will not cause an Address Error exception for unaligned addresses.

An unaligned load/store instruction may be implemented using more than one memory transaction.It is possible for a subset of these memory transactions to have completed and then for a TLB exception to

occur on a remaining transaction.It is also possible that memory could be modified by another thread or device in between the completion of the memory transactions. This behavior is equivalent to what

might occur if the unaligned load/store was carried out in software using a series of separate aligned instructions, for instance using LWL/LWR on a pre-R6 MIPS™ core. Software should take equivalent

steps to accommodate this lack of guaranteed atomicity as it would for the multiple instruction case.

Exceptions:

Bus Error. Reserved Instruction on NMS cores. TLB Invalid. TLB Modified. TLB Refill. Watch.