Encoding:

Format:

DMT rt

Purpose:

Disable Multi-Threaded Execution

To return the previous value of the VPEControl register (see Section 6.5) and disable multi-threaded execution. If

DMT is specified without an argument, GPR r0 is implied, which discards the previous value of the VPEControl register.

Description:

GPR[rt] = VPEControl; VPEControlTE = 0

The current value of the VPEControl register is loaded into general register rt. The Threads Enable (TE) bit in the

VPEControl register is then cleared, suspending concurrent execution of instruction streams other than that which

issues the DMT. This is independent of any per-TC halted state.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation:

This operation specification is for the general multi-threading enable/disable operation, with the sc (set/clear) field as a variable. The individual instructions EMT and DMT have a specific value for the sc field.

if IsCoprocessorEnabled(0) then
   if Config3MT then
      data = VPEControl
      GPR[rt] = data
      VPEControlTE = sc
   else
      SignalException(ReservedInstruction)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Implementation Notes:

DMT accesses a COP0 register and assumes a hard-coded value of rd=1 and sel=1 for VPEControl.

The sc field indicates whether the operation is a bit clear or set, as follows:

Operation

Clear bit specified by the pos field

0

Set bit specified by the pos field

1

Instruction exception checks excluded for clarity) is:

data = CPR[0,rd, sel]
GPR[rt] = data
CPR[0, rd, sel]pos = sc

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading VPEControl into a GPR, clearing the TE bit to create a temporary value in a second GPR, and writing that value back to VPEControl. Unlike the multiple instruction sequence, however, the DMT instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception.

The effect of a DMT instruction may not be instantaneous. An instruction hazard barrier, e.g., JR.HB, is required to guarantee that all other threads have been suspended. If a DMT instruction is followed in the same instruction stream by an MFC0 or MFTR from the VPEControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the DMT and the read of VPEControl to guarantee that the new state of TE will be accessed by the read.