Encoding:

Format:

ADDQ_S.W rd, rs, rt

Purpose:

Add Fractional Words

Addition of two Q31 fractional values to produce a Q31 fractional result, with saturation.

Description:

rd = sat32(rs31..0 + rt31..0)

The Q31 fractional word in register rt is added to the corresponding fractional word in register rs. The result is then written to the destination register rd.

Signed saturating arithmetic is used, where an overflow is clamped to the largest representable value (0x7FFFFFFF hexadecimal) and an un derflow to the smallest representable value (0x80000000 hexadecimal) before being signextended and written to the destination register rd.

If the addition results in underflow, overflow, or saturation, a 1 is written to bit 20 in the DSPControl register within the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ValidateAccessToDSPResources()
temp31..0 = satAdd32( GPR[rs]31..0 , GPR[rt]31..0 )
GPR[rd]31..0 = temp31..0
function satAdd32( a31..0, b31..0 )
   temp32..0 = ( a31 || a31..0 ) + ( b31 || b31..0 )
   if ( temp32 != temp31 ) then
      if ( temp32 = 0 ) then
          temp31..0 = 0x7FFFFFFF
      else
          temp31..0 = 0x80000000
      endif
      DSPControlouflag:20 = 1
   endif
   return temp31..0
endfunction satAdd32

Exceptions:

Reserved Instruction, DSP Disabled