Encoding:

001000

rt

00001

00

001

sc

1

1010110

000

6

5

5

2

3

1

7

3

Format:

EMT rt

MIPS MT

Enable Multi-Threaded Execution

Purpose:

Enable Multi-Threaded Execution

To return the previous value of the VPEControl register (see Section 6.5) and to enable multi-threaded execution. If

EMT is specified without an argument, GPR r0 is implied, which discards the previous value of the VPEControl register.

Description:

GPR[rt] = VPEControl; VPEControlTE = 1

The current value of the VPEControl register is loaded into general register rt. The Threads Enable (TE) bit in the

VPEControl register is then set, allowing multiple instruction streams to execute concurrently.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation:

This operation specification is for the general multi-threading enable/disable operation, with the sc (set/clear) field as a variable. The individual instructions EMT and DMT have a specific value for the sc field.

if IsCoprocessorEnabled(0) then
   if Config3MT then
      data = VPEControl
      GPR[rt] = data
      VPEControlTE = sc
   else
      SignalException(ReservedInstruction)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Implementation Notes:

EMT accesses a COP0 register and assumes a hard-coded value of rd=1 and sel=1 for VPEControl.

The sc field indicates whether the operation is a bit clear or set, as follows:

scOperation

Clear bit specified by the pos field

0

Set bit specified by the pos field

1

The general description of the final operation provided by this operation (with Coprocessor Unusable and Reserved

Instruction exception checks excluded for clarity) is:

data = CPR[0,rd, sel]
GPR[rt] = data
CPR[0, rd, sel]pos = sc

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading VPEControl into a GPR, setting the TE bit to create a temporary value in a second GPR, and writing that value back to VPEControl. Unlike the multiple instruction sequence, however, the EMT instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception.

If an EMT instruction is followed in the same instruction stream by an MFC0 or MFTR from the VPEControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the EMT and the read of VPEControl to guarantee that the new state of TE will be accessed by the read.