Assembly:

MFHC0 rt, c0s, sel

Purpose:

Move From High Coprocessor 0. Write bits 63..32 (when present) of CP0 register indexedby c0s, sel to register $rt.

Availability:

nanoMIPS, required.

(Optional on NMS cores). Requires CP0 privilege.

Format:

Operation:

if C0.Config5.MVH == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
value = read_cp0_register(c0s, sel, h=True)
GPR[rt] = sign_extend(value, from_nbits=32)

For certain core configurations, specific nanoMIPS32™ CP0 registers may be extended to be 64 bits wide. The MFHC0 instruction is used to read the upper 32 bits of such registers. An MFHC0 which

targets a register for which the ’high’ bits are not used will return zero.

This instruction is available when Config5.MVH=1, which is required on nanoMIPS™ cores, except for NMS cores where it is optional.

Exceptions:

Coprocessor Unusable. Reserved Instruction on NMS cores without MVH support.