Assembly:

PREF hint, offset(rs)

PREFE hint, offset(rs)

Purpose:

Prefetch/Prefetch using EVA addressing. Perform a prefetch operation of type hint at address $rs + offset (register plus immediate). For PREFE, translate the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS, availability varies by format.

Format:

PREF[S9]

offset = sign_extend(s, from_nbits=9)
is_eva = False

PREF[U12]

offset = u
is_eva = False

PREFE, present when Config5.EVA=1, requires CP0 privilege.

312625212016151411109870

with hint!=31

offset = sign_extend(s, from_nbits=9)
is_eva = True

Operation:

if is_eva and not C0.Config5.EVA:
    raise exception('RI')
if is_eva and not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=is_eva)
# Perform implementation dependent prefetch actions
pref(va, hint, eva=is_eva)

The PREF and PREFE instructions request that the processor take some action to improve program performance in accordance with the intended data usage specified by the hint argument.This is

typically done by moving data to or from the cache at the specified address. The meanings of hint are as follows:

•      hint=0:
  

load

–

Use: Prefetched data is expected to be read (not modified).

–

Action: Fetch data as if for a load.

• hint=1: store
  

–

Use: Prefetched data is expected to be stored or modified.

–

Action: Fetch data as if for a store.

• hint=2: L1 LRU hint
  

–

Mark the line as LRU in the L1 cache and thus preferred for next eviction.

Implementations can choose to writeback and/or invalidate the line as long as no architectural state is

modified.

• hint=3: Reserved for Implementation
  

• hint=4:
  

load_streamed

–

Use: Prefetched data is expected to be read (not modified) but not reused extensively;

it

”streams” through cache.

–

Action: Fetch data as if for a load and place it in the cache so that it does not displace data

prefetched as ”retained”.

• hint=5: store_streamed
  

–

Use: Prefetched data is expected to be stored or modified but not reused extensively;

it

”streams” through cache.

–

Action: Fetch data as if for a store and place it in the cache so that it does not displace data

prefetched as ”retained”.

• hint=6:
  

load_retained

–

Use: Prefetched data is expected to be read (not modified) and reused extensively; it should

be ”retained” in the cache.

–

Action: Fetch data as if for a load and place it in the cache so that it is not displaced by data

prefetched as ”streamed”.

• hint=7: store_retained
  

–

Use: Prefetched data is expected to be stored or modified and reused extensively; it should

be ”retained” in the cache.

–

Action: Fetch data as if

for a store and place it in the cache so that it is not displaced by

data prefetched as ”streamed”.

• hint=8..15: L2 operation
  

–

In the Release 6 architecture, hint codes 8..15 are treated the same as hint codes 0..7 respectively, but operate on the L2 cache.

• hint=16..23: L3 operation
  

–

In the Release 6 architecture, hint codes 16..23 are treated the same as hint codes 0..7 respectively, but operate on the L3 cache.

• hint=24..30: Reserved for Architecture
  

–

These hint codes are reserved in nanoMIPS and should act as a NOP. (This is not the same

as the MIPSR6 behavior, where these hints give a Reserved Instruction exception). Note that hint=31 is not listed as that encoding is decoded as a SYNCI instruction.

The action taken for a specific PREF instruction is both system and context dependent. Any action, including doing nothing, is permitted as long as it does not change architecturally visible state or alter

the meaning of a program.

PREF does not cause addressing-related exceptions, including TLB exceptions.If the address specified would cause an addressing exception, the exception condition is ignored and no data movement occurs.

For cached addresses, the expected and useful action is for the processor to prefetch a block of data that includes the effective address. The size of the block and the level of the memory hierarchy it is

fetched into are implementation specific.

PREF neither generates a memory operation nor modifies the state of a cache line for addresses with an uncached CCA.

Prefetch operations have no effect on cache lines that were previously locked with the CACHE instruction.

In coherent multiprocessor implementations,if the effective address uses a coherent CCA, then the instruction causes a coherent memory transaction to occur.This means a prefetch issued on one

processor can cause data to be evicted from the cache in another processor.

The memory transactions which occur as a result of a PREF instruction, such as cache refill or cache writeback, obey the same ordering and completion rules as other load or store instructions.

It is implementation dependent whether a Bus Error or Cache Error exception is reported if such an error is detected as a byproduct ofthe action taken by the PREF instruction.Implementations are

encouraged to report such errors only if there is a specific requirement for high-reliability. Note that

suppressing a bus or cache error in this case may require that the processor communicate to the system that the reference is speculative.

Hint field encodings whose function is described as ”streamed” or ”retained” convey usage intent from software to hardware. Software should not assume that hardware will always prefetch data in an

optimal way.If data is to be truly retained, software should use the Cache instruction to lock data into the cache.

Itis implementation dependent whether a data watch or EJTAG breakpoint exception is triggered by a prefetch instruction whose address matches the Watch register address match or EJTAG data

breakpoint conditions. The preferred implementation is not to match on the prefetch instruction.

Exceptions:

Bus Error. Cache Error. Coprocessor Unusable for PREFE. Reserved Instruction for PREFE if EVA not implemented.