TLBWR |
nanoMIPS. Required on TLB cores. Requires CP0 privilege. |
TLB Write Random |
TLB Write Random. Write a randomly chosen TLB entry using the values in the TLB CP0registers EntryHi, EntryLo0, EntryLo1, PageMask.
nanoMIPS. Required on TLB cores. Requires CP0 privilege.
|
001000 |
x |
00 |
11001 |
101 |
111 |
111 |
|
6 |
10 |
2 |
5 |
3 |
3 |
3 |
if not got_tlb():
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
tlbwr()
Coprocessor Unusable. Reserved Instruction if TLB not implemented.