Assembly: 

SW rt, offset(rs)

nanoMIPS, availability varies by format.

Store Word

Purpose:

Store Word. Store word from register $rt to memory address $rs + offset (register plusimmediate).

Availability:

nanoMIPS, availability varies by format.

Format:

SW[U12]

100001

rt

rs

1001

u

6

5

5

4

12 

offset = u

SW[16]

100101

rtz3

rs3

u[5:2]

6

3

3

4 

rt = decode_gpr(rtz3, 'gpr3.src.store')
rs = decode_gpr(rs3, 'gpr3')
offset = u

SW[4X4], not available in NMS

111101

rtz4[3]

u[2]

rtz4[2:0]

rs4[3]

u[3]

rs4[2:0]

6

1

1

3

1

1

3 

if C0.Config5.NMS == 1:
    raise exception('RI')
rt = decode_gpr(rtz4[3] @ rtz4[2:0], 'gpr4.zero')
rs = decode_gpr(rs4[3] @ rs4[2:0], 'gpr4')
offset = u

SW[GP]

010000

rt

u[20:2]

11

6

5

19

2 

rs = 28
offset = u

SW[GP16]

110101

rtz3

u[8:2]

6

3

7 

rt = decode_gpr(rtz3, 'gpr3.src.store')
rs = 28
offset = u

SW[S9]

101001

rt

rs

s[8]

1001

0

00

s[7:0]

6

5

5

1

4

1

2

8 

offset = sign_extend(s, from_nbits=9)

SW[SP]

101101

rt

u[6:2]

6

5

5 

rs = 29
offset = u

Operation: 

va = effective_address(GPR[rs], offset, 'Store')
data = zero_extend(GPR[rt], from_nbits=32)
write_memory_at_va(data, va, nbytes=4)

Exceptions:

Address Error. Bus Error. Reserved Instruction for SW[4X4] format on NMS Cores. TLB Invalid. TLB Modified. TLB Refill. Watch.