Assembly: 

ADDIU rt, rs, imm

nanoMIPS, availability varies by format.

Add Immediate (Untrapped)

Purpose:

Add Immediate (Untrapped). Add immediate value imm to the 32-bit integer value in register$rs, placing the 32-bit result in register $rt, and not trapping on overflow.

Availability:

nanoMIPS, availability varies by format.

Format:

ADDIU[32]

000000

rt!=0

rt

rs

u

6

5

5

16 

imm = u

ADDIU[48], not available in NMS

011000

rt

00001

s[15:0]

s[31:16]

6

5

5

16

16 

if C0.Config5.NMS == 1:
    raise exception('RI')
imm = sign_extend(s, from_nbits=32)
rs = rt

ADDIU[GP48], not available in NMS, not available in P64 mode

011000

rt

00010

s[15:0]

s[31:16]

6

5

5

16

16 

if C0.Config5.NMS == 1:
    raise exception('RI')
if pointers_are_64_bits():
    raise behaves_like('DADDIU[GP48]')
imm = sign_extend(s, from_nbits=32)
rs = 28

ADDIU[GP.B], not available in P64 mode

010001

rt

011

u

6

5

3

18 

if pointers_are_64_bits():
    raise behaves_like('DADDIU[GP.B]')
imm = u
rs = 28

ADDIU[GP.W], not available in P64 mode

010000

rt

u[20:2]

00

6

5

19

2 

if pointers_are_64_bits():
    raise behaves_like('DADDIU[GP.W]')
imm = u
rs = 28

ADDIU[R1.SP], not available in P64 mode

011100

rt3

1

u[7:2]

6

3

1

6 

if pointers_are_64_bits():
    raise behaves_like('DADDIU[R1.SP]')
rt = decode_gpr(rt3, 'gpr3')
rs = 29
imm = u

ADDIU[R2]

100100

rt3

rs3

0

u[4:2]

6

3

3

1

3 

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
imm = u

ADDIU[RS5]

100100

with rt!=0

rt

s[3]

1

s[2:0]

6

5

1

1

3 

rs = rt
imm = sign_extend(s, from_nbits=4)

ADDIU[RS5] with rt=0 is used to provide a 16 bit NOP instruction.

ADDIU[NEG]

100000

rt

rs

1000

u

6

5

5

4

12 

imm = -u

Operation: 

sum = GPR[rs] + imm
GPR[rt] = sign_extend(sum, from_nbits=32)

Exceptions:

Reserved Instruction for ADDIU[48] and ADDIU[GP48] formats on NMS cores.