Encoding:

Format:

MULTU ac, rs, rt 

Purpose:

Multiply Unsigned Word

To multiply 32-bit unsigned integers, writing the 64-bit result to the specified accumulator.

Description:

 ac = rs31..0 * rt31..0

The 32-bit unsigned integer value in register rt is multiplied by the corresponding 32-bit unsigned integer value in register rs, to produce a 64-bit unsigned result that is written to the specified accumulator register.

The value of ac selects an accumulator numbe red from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS32 architecture.

In Release 6 of the MIPS Architecture, accumulators are eliminated from MIPS32.

No arithmetic exception occurs under any circumstances.

Restrictions:

None

Operation:

if (( ac != 0 ) or (ConfigAR >= )) then 
   ValidateAccessToDSP2Resources()
endif
temp64..0 = ( 032 || GPR[rs]31..0 ) * ( 032 || GPR[rt]31..0 ) 
( HI[ac]31..0 || LO[ac]31..0 ) = temp63..32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

In some processors the integer multiply operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not af fect the program result, but offers an opportunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.

Programs that require overflow detection must check for it explicitly.

Where the size of the operands are known, software should place the shorter operand in register rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

Implementation Note:

Processors which implement a multiplier array which is not square (for example, 32 x 16), and which therefore has an operation latency which is data dependent, should assume that the shorter operand is in register rt.