Assembly:

MTHC0 rt, c0s, sel

Purpose:

Move To High Coprocessor 0. Write value of register $rt to bits 63..32 (when present) ofCP0 register indexed by c0s, sel.

Availability:

nanoMIPS, required.

(Optional on NMS cores). Requires CP0 privilege.

Format:

Operation:

if C0.Config5.MVH == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
write_cp0_register(GPR[rt], c0s, sel, h=True)

For certain core configurations, specific nanoMIPS32™ CP0 registers may be extended to be 64 bits wide.The MTHC0 instruction is used to write the upper 32 bits of such registers. An MTHC0 to a

register for which the ’high’ bits are not used will be ignored.

When a register is extended to have high bits for a specific configuration, legacy software which is not aware of the existence of these high bits still needs to function correctly.In such cases, the architecture

may require that an MTC0 modifies the high 32 bits of the register as well as the low 32 bits to give the correct legacy behavior.

For this reason, when setting an extended CP0 register, the MTC0 to set the low 32 bits should always precede the MTHC0 to set the high 32 bits. Also, a read-modify-write sequence to set a specific bitfield

in the low 32 bits should read both the low 32 and high 32 bits, then do MTC0 followed by MTHC0 to write the modified value back.

This instruction is available when Config5.MVH=1, which is required on nanoMIPS™ cores, except for NMS cores where it is optional.

Exceptions:

Coprocessor Unusable. Reserved Instruction on NMS cores without MVHm support.