Assembly:

MTC0 rt, c0s, sel

Purpose:

Move To Coprocessor 0. Write value of register $rt to CP0 register indexed by c0s, sel.

Availability:

nanoMIPS. Requires CP0 privilege.

Format:

Operation:

if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
write_cp0_register(GPR[rt], c0s, sel)

An MTC0 to a register which is not used on the current core is ignored.

When a register is extended to have high bits for a specific configuration (see MTHC0), legacy software which is not aware of the existence of these high bits still needs to function correctly.In such cases,

the architecture may require that an MTC0 modifies the high 32 bits of the register as well as the low 32 bits to give the correct legacy behavior.

For this reason, when setting an extended CP0 register, the MTC0 to set the low 32 bits should always precede the MTHC0 to set the high 32 bits. Also, a read-modify-write sequence to set a specific bitfield

in the low 32 bits should read both the low 32 and high 32 bits, then do MTC0 followed by MTHC0 to write the modified value back.

Exceptions:

Coprocessor Unusable.