INS rt, rs, pos, size - Insert. Merge a right justiﬁed bit ﬁeld of size size from register $rs into position pos of

Assembly:

INS rt, rs, pos, size

nanoMIPS, not available in NMS

Insert. Merge a right justiﬁed bit ﬁeld of size size from register $rs into position pos of

Purpose:

Insert. Merge a right justiﬁed bit ﬁeld of size size from register $rs into position pos of

Availability:

nanoMIPS, not available in NMS

Format:

100000	rt	rs	1110	0	msbd	0	lsb
6	5	5	4	1	5	1	5

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
pos = lsb
size = 1 + msbd - lsb
if size < 1:
    raise UNPREDICTABLE()
merge_mask = ((1<<size) - 1) << pos
result = (GPR[rt] & ~merge_mask
          | (GPR[rs] << pos) & merge_mask)
GPR[rt] = sign_extend(result, from_nbits=32)

The INS instruction is not available on NMS cores.It can be emulated using a sequence of three EXTW instructions:

       INS      rt, rs, pos, size

can be emulated using the following sequence of instructions (provided rt is not equal to rs):

       EXTW     rt, rt, rt, pos
       EXTW     rt, rt, rs, size
       EXTW     rt, rt, rt, 32 size -pos

Exceptions:

Reserved Instruction on NMS cores.