SBX rd, rs(rt) |
nanoMIPS, not available in NMS |
Store Byte indeXed |
Store Byte indeXed. Store byte from register $rt to memory address $rt + $rs (registerplus register).
nanoMIPS, not available in NMS
001000 |
rt |
rs |
rd |
0001 |
0 |
000 |
111 |
6 |
5 |
5 |
5 |
4 |
1 |
3 |
3 |
if C0.Config5.NMS == 1: raise exception('RI') va = effective_address(GPR[rs], GPR[rt], 'Store') data = zero_extend(GPR[rd], from_nbits=8) write_memory_at_va(data, va, nbytes=1)
Address Error. Bus Error. Reserved Instruction on NMS cores. TLB Invalid. TLB Modified. TLB Refill. Watch.