NOP |
nanoMIPS |
No Operation |
No Operation.
nanoMIPS
|
100000 |
00000 |
x |
1100 |
x |
0000 |
00000 |
|
6 |
5 |
5 |
4 |
3 |
4 |
5 |
|
100100 |
00000 |
x |
1 |
x |
|
6 |
5 |
1 |
1 |
3 |
# No operation pass
The NOP[32] encoding is equivalent to an SLL[32] instruction using $0 as output and a shift value of 0. The NOP[16] encoding is equivalent to an ADDIU[RS5] instruction using $0 as output. Therefore NOP
does not necessarily need any additionalimplementation in hardware beyond the normal behavior of the SLL[32] and ADDIU[RS5] instructions.
If software intentionally generates a NOP instruction, it should only generate these specific encodings, rather than other instructions writing to $0 which would also result in no operation.
If hardware implements a performance counter for nops,it can expect these specific instruction encodings to be used.
It should ignore the x field of the encoding, treating all values of x as representing
a valid NOP instruction. Software on the other hand should only generate NOP instructions with an x value of 0.
As for all instruction definitions containing x fields, this methodology allows for the possibility that the meaning of x values other than zero might be enhanced in the future, with the understanding that cores
prior to the enhanced definition will treat the x!=0 encodings as equivalent to the x==0 instruction.
None.