Encoding:

P32A

001000

rt

rs

sa

001

111

111

111

6

5

5

4

3

3

3

3

Format: 

SHRL.PH rt, rs, sa

DSP-R2

Shift Right Logical Two Halfwords

Purpose:

Shift Right Logical Two Halfwords

To execute a right shift of two independent halfwords in a vector data type by a fixed number of bits.

Description: 

rt = (rs31..16 >> sa) || (rs15..0 >> sa)

The two halfwords in register rs are independently logically shifted right, inserting zeros into the bit positions emptied by the shift. The two halfword results are then written to the corresponding halfword elements in destination register rt.

The shift amount is provided by the sa field, which is interpreted as a four bit unsigned integer taking values between

0 and 15.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

ValidateAccessToDSP2Resources()
tempB15..0 = 0sa || GPR[rs]31..sa+16 
tempA15..0 = 0sa || GPR[rs]15..sa 
GPR[rt]31..0 = tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled