Encoding:

P32A

001000

rt

rs

rd

x

0010101

101

6

5

5

5

1

7

3

Format: 

PRECRQ.QB.PH rd, rs, rt

DSP

Precision Reduce Four Fractional Halfwords to Four Bytes

Purpose:

Precision Reduce Four Fractional Halfwords to Four Bytes

Reduce the precision of four fractional halfwords to four byte values.

Description: 

rd = rs31..24 || rs15..8 || rt31..24 || rt15..8

The four Q15 fractional values in registers rs and rt are truncated by dropping the eight least significant bits from each value to produce four fractional byte values. The four fractional byte values are written to the four byte elements of destination register rd. The two values obtained from register rt are placed in the two right-most byte positions in the destination register, and the two values obtained from register rs are placed in the two remaining byte positions.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

ValidateAccessToDSPResources()
tempD7..0 = GPR[rs]31..24
tempC7..0 = GPR[rs]15..8
tempB7..0 = GPR[rt]31..24
tempA7..0 = GPR[rt]15..8
GPR[rd]31..0 = tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0

Exceptions:

Reserved Instruction, DSP Disabled