ADDU dst, src1, src2 |
nanoMIPS, availability varies by format. |
Add (Untrapped) |
Add (Untrapped). Add two 32-bit integers in registers $src1 and $src2, placing the 32-bitresult in register $dst, and not trapping on overflow.
nanoMIPS, availability varies by format.
|
001000 |
rt |
rs |
rd |
x |
0101010 |
000 |
|
6 |
5 |
5 |
5 |
1 |
7 |
3 |
dst = rd src1 = rs src2 = rt not_in_nms = False
|
101100 |
rt3 |
rs3 |
rd3 |
0 |
|
6 |
3 |
3 |
3 |
1 |
dst = decode_gpr(rd3, 'gpr3') src1 = decode_gpr(rs3, 'gpr3') src2 = decode_gpr(rt3, 'gpr3') not_in_nms = False
|
001111 |
rt4[3] |
0 |
rt4[2:0] |
rs4[3] |
0 |
rs4[2:0] |
|
6 |
1 |
1 |
3 |
1 |
1 |
3 |
dst = decode_gpr(rt4, 'gpr4') src1 = decode_gpr(rt4, 'gpr4') src2 = decode_gpr(rs4, 'gpr4') not_in_nms = True
if not_in_nms and C0.Config5.NMS:
raise exception('RI')
sum = GPR[src1] + GPR[src2]
GPR[dst] = sign_extend(sum, from_nbits=32)
Reserved Instruction for ADDU[4X4] format on NMS cores.