Encoding:

Format:

INSV rt, rs

Purpose:

Insert Bit Field Variable

To merge a right-justified bit field from register rs into a specified field in register rt.

Description:

rt = InsertFieldVar(rt, rs, Scount, Pos)

The DSPControl register provides the size value from the Scount field, and the pos value from the pos field. The rightmost size bits from register rs are merged into the value from register rt starting at bit position pos. The result is put back in register rt. These pos and size values are converted by the instruction into the fields msb (the most significant bit of the field), and lsb (least significant bit of the field), as follows:

pos = DSPControl5..0
size = DSPControl12..7
msb = pos+size-1
lsb = pos

The values of pos and size must satisfy all of the following relations, or the instruction results in UNPREDICTABLE results:

0 <= pos < 32
0 < size <= 32
0 < pos+size <= 32

Restrictions:

The operation is UNPREDICTABLE if lsb > msb.

Operation:

ValidateAccessToDSPResources()
if (lsb > msb) then

UNPREDICTABLE
endif
GPR[rt]31..0 = GPR[rt]31..msb+1 || GPR[rs]msb-lsb..0 || GPR[rt]lsb-1..0

Exceptions:

Reserved Instruction, DSP Disabled

Implementation Notes

The destination of this instruction is register rt because that register is used as both a source and destination of the instruction. Since most implementations have potential critical paths around source register decode, and typically decode registers rs and rt as source registers, the instruction is defined with the destination as register rt instead of register rd to minimize the impact on source register decode.

One implementation method is to shift the register rs value left by lsb bits and merge that value into the register rt value based on a merge mask. The merge mask has a 1 in every bit position from which the corresponding output bit comes from register rs and a 0 in every bit position from which the corresponding output bit comes from register rt.

The mask can be calculated by subtracting two constants generated from the fields of the instruction, as follows:

k1 = 032-lsb-1 || 1 || 0lsb
k2 = (033-(msb+2) || 1 || 0msb+1)31..0
merge_mask = k2 - k1

Some implementations may choose to use the ALU to calculate the merge_mask in parallel with shifting the register

rs value to the left, then using the merge_mask to bit-select from the register rt value or the shifted register rs value.