Encoding:

Format:

DVPE rt

Purpose:

Disable Virtual Processor Execution

To return the previous value of the MVPControl register (see Section 6.2) and disable multi-VPE execution. If DVPE is specified without an argument, GPR r0 is implied, which discards the previous value of the MVPControl register.

Description:

GPR[rt] = MVPControl; MVPControlEVP = 0

The current value of the MVPControl register is loaded into general register rt. The Enable Virtual Processors (EVP) bit in the MVPControl register is then cleared, suspending concurrent execution of instruction streams other than the instruction stream that issues the DVPE.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation:

This operation specification is for the general VPE enable/disable operation, with the sc (set/clear) field as a variable.

The individual instructions EVPE and DVPE have a specific value for the sc field.

if IsCoprocessorEnabled(0) then
   if Config3MT then
      data = MVPControl
      GPR[rt] = data
      if(VPEConf0MVP = 1) then
         MVPControlEVP = sc
      endif
   else
      SignalException(ReservedInstruction)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Implementation Notes:

DVPE accesses a COP0 register and assumes a hard-coded value of rd=0 and sel=1 for MVPControl.

The sc field indicates whether the operation is a bit clear or set, as follows:

scOperation

0Clear bit specified by the pos field

1Set bit specified by the pos field

The general description of the final operation provided by this operation (with Coprocessor Unusable and Reserved

Instruction exception checks excluded for clarity) is:

data = CPR[0,rd, sel]
GPR[rt] = data
CPR[0, rd, sel]pos = sc

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading MVPControl into a GPR, clearing the EVP bit to create a temporary value in a second GPR, and writing that value back to MVPControl. Unlike the multiple instruction sequence, however, the DVPE instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception, nor by the scheduling of a different instruction stream.

The effect of a DVPE instruction may not be instantaneous. An instruction hazard barrier, e.g., JR.HB, is required to guarantee that all other TCs have been suspended.

If a DVPE instruction is followed in the same instruction stream by an MFC0 or MFTR from the MVPControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the DVPE and the read of MVPControl to guarantee that the new state of EVP will be accessed by the read.