Assembly:

SHE rt, offset(rs)

Purpose:

Store Half using EVA addressing. Store halfword from register $rt to virtual address $rs+ offset, translating the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege.

Format:

Operation:

offset = sign_extend(s, from_nbits=9)
if not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Store', eva=True)
data = zero_extend(GPR[rt], from_nbits=16)
write_memory_at_va(data, va, nbytes=2, eva=True)

Exceptions:

Address Error. Bus Error. Coprocessor Unusable. Reserved Instruction if EVA not implemented. TLB Invalid. TLB Modified. TLB Refill. Watch.