Encoding:

P32A

001000

rt

rs

1111000

100

111

111

6

5

5

7

3

3

3

Format: 

RADDU.W.QB rt, rs

DSP

Unsigned Reduction Add Vector Quad Bytes

Purpose:

Unsigned Reduction Add Vector Quad Bytes

Reduction add of four unsigned byte values in a vector register to produce an unsigned word result.

Description: 

rt = zero_extend(rs31..24 + rs23..16 + rs15..8 + rs7..0)

The unsigned byte elements in register rs are added together as unsigned 8-bit values, and the result is zero extended to a word and written to register rt.

Restrictions:

No data-dependent exceptions are possible.

The operands must be in the specif ied format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

ValidateAccessToDSPResources()
temp9..0 = ( 02 || GPR[rs]31..24 ) + ( 02 || GPR[rs]23..16 ) + ( 02 || GPR[rs]15..8 ) + 
( 02 || GPR[rs]7..0 )
GPR[rt]31..0 = 0(GPRLEN-10) || temp9..0

Exceptions:

Reserved Instruction, DSP Disabled