ROTX rt, rs, shift, shiftx, stripe |
nanoMIPS, not available in NMS |
Rotate and eXchange |
Rotate and eXchange. Rotate and exchange bits in the word value in register $rs and placeresult in register $rt. Specific choices of the shift, shiftx and stripe arguments allow this instruction to perform bit and byte reordering operations including BYTEREVW, BYTEREVH, BITREVW, BITREVH
and BITREVB.
nanoMIPS, not available in NMS
|
100000 |
rt |
rs |
1101 |
0 |
shiftx[4:1] |
stripe |
0 |
shift |
|
6 |
5 |
5 |
4 |
1 |
4 |
1 |
1 |
5 |
if C0.Config5.NMS:
raise exception('RI')
tmp0 = GPR[rs][31:0] @ GPR[rs][31:0]
tmp1 = tmp0
for i in range(47): # 0..46
s = shift if (i & 0b01000) else shiftx
if stripe and not (i & 0b00100): s = ~s
if s[4]: tmp1[i] = tmp0[i+16]
tmp2 = tmp1
for i in range(39): # 0..38
s = shift if (i & 0b00100) else shiftx
if s[3]: tmp2[i] = tmp1[i+8]
tmp3 = tmp2
for i in range(35): # 0..34
s = shift if (i & 0b00010) else shiftx
if s[2]: tmp3[i] = tmp2[i+4]
tmp4 = tmp3
for i in range(33): # 0..32
s = shift if (i & 0b00001) else shiftx
if s[1]: tmp4[i] = tmp3[i+2]
tmp5 = tmp4
for i in range(32): # 0..31
s = shift;
if s[0]: tmp5[i] = tmp4[i+1]
GPR[rt] = sign_extend(tmp5, from_nbits=32)
The ROTX instruction can be used to reverse elements of a selected size within blocks of a different selected size. Some example use cases are shown in the table below. The ’Result’ shows the output value
assuming an input value of abcdefgh ijklmnopqrstuvwx yz012345, where each character represents the value of a single bit.
Assembly/Result from
abcdefgh ijklmnop qrstuvwx
AliasOperationyz012345
BITREVWReverse all bitsROTX rt, rs, 31, 0
543210zy xwvutsrq ponmlkji
hgfedcba
BITREVHReverse bits in halfsROTX rt, rs, 15, 16
ponmlkji hgfedcba 543210zy
xwvutsrq
BITREVBReverse bits in bytesROTX rt, rs, 7, 8, 1
hgfedcba ponmlkji xwvutsrq
543210zy
BYTEREVWReverse all bytesROTX rt, rs, 24, 8
yz012345 qrstuvwx ijklmnop
abcdefgh
BYTEREVHReverse bytes in halfsROTX rt, rs, 8, 24
ijklmnop abcdefgh yz012345
qrstuvwx
Reverse all nibblesROTX rt, rs, 28, 4
2345yz01 uvwxqrst mnopijkl
efghabcd
Reverse nibbles in halfsROTX rt, rs, 12, 20
mnopijkl efghabcd 2345yz01
uvwxqrst
Reverse nibbles in bytesROTX rt, rs, 4, 12, 1
efghabcd mnopijkl uvwxqrst
Assembly/Result from
abcdefgh ijklmnop qrstuvwx
AliasOperationyz012345
Reverse all bit pairsROTX rt, rs, 30, 2
452301yz wxuvstqr opmnklij
ghefcdab
Reverse pairs in halfsROTX rt, rs, 14, 18
opmnklij ghefcdab 452301yz
wxuvstqr
Reverse pairs in bytesROTX rt, rs, 6, 10, 1
ghefcdab opmnklij wxuvstqr
452301yz
Assembler aliases are provided for certain cases, as indicated in the table.
The MIPS32™ instructions BITSWAP and WSBH are equivalent to BITREVB and BYTEREVH respectively, and are also provided as assembler aliases to ROTX.
The ROTX instruction is designed to be implementable with minimal overhead using existing logic for the ROTR instruction. ROTR can be implemented using a barrel shifter, where the select signals for
the multiplexers at each stage are the bits of the ’shift’ argument. For ROTX, the mux select signals depend on the bit position as well as the stage of the shifter, and are a function of the ’shift’,’shiftx’
and ’stripe’ arguments.
Reserved Instruction on NMS cores.