Assembly:

DERET

Purpose:

Debug Exception Return. Return from a debug exception by jumping to the address in theDEPC register, and clearing Debug.DM.

Availability:

nanoMIPS. Optional, present when Debug implemented.

Format:

Operation:

if C0.Config1.EP == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if C0.Debug.DM == 0:
    raise exception('RI')
CPU.next_pc = sign_extend(Root.C0.DEPC)
C0.Debug.DM = 0
# If single stepping, forward progress isallowedonthenextinstruction.
CPU.debug_sst_progress_allowed = True
clear_execution_hazards()
clear_instruction_hazards()

The DERET instruction implements a software barrier that resolves all execution and instruction hazards. See the EHB and JALRC.HB instructions for an explanation of execution and instruction hazards

respectively, and also the SYNCI/SYNCIE instruction for additionalinformation on resolving instruction hazards created by writing to the instruction stream.

The effects of the DERET barrier are seen starting with the fetch and decode of the instruction at the PC to which the DERET returns. This means,for instance,that if C0.DEPC is modified by an MTC0

instruction prior to a DERET, an EHB is required between the MTC0 and the DERET to ensure that the DERET uses the correct DEPC value.

The DERET instruction is only legalin debug mode and will give a Coprocessor Unusable exception when executed in user mode or a Reserved Instruction exception when executed in kernel mode.

Exceptions:

Coprocessor Unusable.Reserved Instruction when notin Debug Mode or on cores without Debug support.