Assembly:

LWM rt, offset(rs), count

Purpose:

Load Word Multiple. Load count words of data to registers $rt, $(rt+1),

..., $(rt+count-1)

from consecutive memory address starting at $rs + offset (register plus immediate).

Availability:

nanoMIPS, not available in NMS

Format:

offset = sign_extend(s, from_nbits=9)
count = 8 if count3 == 0 else count3

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
i = 0
while i != count:
    this_rt = ( rt + i      if rt + i < 32 else
                rt + i - 16                    )
    this_offset = offset + (i<<2)
    va = effective_address(GPR[rs], this_offset, 'Load')
    data = read_memory_at_va(va, nbytes=4)
    GPR[this_rt] = sign_extend(data, from_nbits=32)
    if this_rt == rs and i != count - 1:
        raise UNPREDICTABLE()
    i += 1

LWM loads count words to sequentially numbered register from sequential memory addresses. After loading $31, the sequence of registers continues from $16. Some example encodings of the register

list are:

• rt=15, count=3:

loads [$15, $16, $17]

• rt=31, count=3:

loads [$31, $16, $17].

The result is unpredictable if an LWM instruction updates the base register prior to the final load.

LWM must be implemented in such a way as to make the instruction restartable, but the implementation does not need to be fully atomic. For instance,it is allowable for a LWM instruction to be aborted by

an exception after a subset of the register updates have occurred. To ensure restartability, any write to GPR $rs (which may be used as the final output register) must be completed atomically, that is, the

instruction must graduate if and only if that write occurs.

Exceptions:

Address Error. Bus Error. Reserved Instruction on NMS cores. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.