CACHE op, offset(rs) - Cache operation/Cache operation using EVA addressing

Assembly:

CACHE op, offset(rs)	nanoMIPS. Requires CP0 privilege, availability varies by format.	Cache operation/Cache operation using EVA addressing
CACHEE op, offset(rs)	nanoMIPS. Requires CP0 privilege, availability varies by format.	Cache operation/Cache operation using EVA addressing

Purpose:

Cache operation/Cache operation using EVA addressing. Perform cache operation of typeop at address $rs +offset (register plus immediate). For CACHEE, translate the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Requires CP0 privilege, availability varies by format.

Format:

CACHE

101001	op	rs	s[8]	0111	0	01	s[7:0]
6	5	5	1	4	1	2	8

offset = sign_extend(s, from_nbits=9)
is_eva = False

CACHEE, present when Conﬁg5.EVA=1.

101001	op	rs	s[8]	0111	0	10	s[7:0]
6	5	5	1	4	1	2	8

offset = sign_extend(s, from_nbits=9)
is_eva = True

Operation:

# NMS core without caches gives RI (not CoprocessorUnusable)exception.
if (C0.Config5.NMS and C0.Config1.DL == 0 and C0.Config1.IL == 0
                   and C0.Config2.SL == 0 and C0.Config2.TL == 0
                   and C0.Config5.L2C == 0):
    raise exception('RI')
if is_eva and not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=is_eva)
# Behavior for index cacheops is unpredictable ifaddressisnotunmapped.
if op <= 11:  # Index cacheop
    translation_type, description, result_args = decode_va(va, eva=is_eva)
    if translation_type != 'unmapped':
        raise UNPREDICTABLE('Index cacheopunpredictable withVA not unmapped')
pa, cca = va2pa(va, 'Cacheop', eva=is_eva)
if cca == 2 or cca == 7:
    if C0.Config.AT >= 2:
        pass  # Cacheop to uncached address is anopin R6
    else:
        raise UNPREDICTABLE('Cacheop to uncached address isunpredictable')
else:
    cacheop(va, pa, op)

The CACHE/CACHEE instructions perform the cache operation speciﬁed by argument ’op’ on the register plus immediate address $rs +offset. For CACHEE, the virtual address is translated as though

the core is in user mode, although it is actually in kernel mode.

The ’op’ argument is a 5 bit value specifying one of the following the possible cache operations, which are described in more detail below:

’op’OperationAvailability

0ICache Index InvalidateRequired (if ICache present) 1DCache Index Writeback InvalidateRequired (if DCache present)

2TCache Index Writeback InvalidateRequired (if TCache present) 3SCache Index Writeback InvalidateRequired (if SCache present)

4ICache Index Load TagRecommended (if ICache present) 5DCache Index Load TagRecommended (if DCache present)

6TCache Index Load TagRecommended (if TCache present) 7SCache Index Load TagRecommended (if SCache present)

8ICache Index Store TagRequired (if ICache present) 9DCache Index Store TagRequired (if DCache present)

10TCache Index Store TagRequired (if TCache present) 11SCache Index Store TagRequired (if SCache present)

12ICache Implementation Dependent OpOptional (if ICache present) 13DCache Implementation Dependent OpOptional (if DCache present)

14TCache Implementation Dependent OpOptional (if TCache present) 15SCache Implementation Dependent OpOptional (if SCache present)

16ICache Hit InvalidateRequired (if ICache present) 17DCache Hit InvalidateOptional (if DCache present)

18TCache Hit InvalidateOptional (if TCache present) 19SCache Hit InvalidateOptional (if SCache present)

20ICache FillRecommended (if ICache present) 21DCache Hit Writeback InvalidateRecommended (if DCache present)

’op’OperationAvailability

22TCache Hit Writeback InvalidateRecommended (if TCache present) 23SCache Hit Writeback InvalidateRecommended (if SCache present)

24Unused 25DCache Hit WritebackRecommended (if DCache present)

26TCache Hit WritebackRecommended (if TCache present) 27SCache Hit WritebackRecommended (if SCache present)

28ICache Fetch and LockRecommended (if ICache present) 29DCache Fetch and LockRecommended (if DCache present)

30Unused 31Unused

Index cacheops (those with op <= 11 and optionally the implementation dependent cases 12<= op <=

15) are operations where the input address is treated as an index into the target cache array. The rules for constructing the index are given in the cacheop() function pseudocode.

’Hit’ cacheops are operations where the input address is treated as a virtual memory address.The operation willtargetthe cache line containing data for that virtual address,ifitis presentin the

cache.

The operations listed above behave as follows:

ICache Index Invalidate (op=0): Set the state of the instruction cache line at the speciﬁed index to invalid.

D/T/S Cache Index Writeback Invalidate (op=1,2,3):

Ifthe cache line atthe speciﬁed index is

valid and dirty, write the line back to the memory address speciﬁed by the cache tag. Whether or not the line was dirty, set the state of the cache line to invalid. For a write-through cache, the

writeback step is not required and this is eﬀectively a Cache Index Invalidate operation. This cache operation is required and may be used by software to invalidate the entire data cache by

stepping through allindices. Note that the Index Store Tag operation must be used to initialize the cache at power up.

I/D/T/S Cache Index Load Tag (op=4,5,6,7): Read the tag for the cache line at the speciﬁed index

into the TagLo and TagHi Coprocessor 0 registers.If the DataLo and DataHi registers are implemented, also read the data corresponding to the byte index into the DataLo and DataHi registers.

This operation must not cause a Cache Error Exception. The granularity and alignment of the data read into the DataLo and DataHi registers is implementation-dependent, but is typically the

result of an aligned access to the cache, ignoring the appropriate low-order bits of the byte index.

I/D/T/S Cache Index Store Tag (op=8,9,10,11): Write the tag for the cache block at the speciﬁed index from the TagLo and TagHi Coprocessor 0 registers. This operation must not cause a Cache

Error Exception. This required encoding may be used by software to initialize the entire instruction or data caches by stepping through all valid indices. Doing so requires that the TagLo and

TagHi registers associated with the cache be initialized to zero ﬁrst.

I/D/T/S Cache Implementation Dependent Op (op=12,13,14,15): Available for implementation dependent operation.

I/D/T/S Cache Hit Invalidate (op=16,17,18,19):

If the cache block contains the speciﬁed address,

setthe state ofthe cache block to invalid.This required encoding may be used by software to invalidate a range of addresses from the instruction cache by stepping through the address

range by the line size of the cache.In multiprocessor implementations with coherent caches, the operation may optionally be broadcast to all coherent caches within the system.

ICache FIll (op=20): Fill the cache from the speciﬁed virtual address.
D/T/S Hit Writeback Invalidate (op=21,22,23): For the cache line (if any) which contains the

speciﬁed address:if the cache line is valid and dirty, write the line back to the memory address speciﬁed by the cache tag. Whether or not the line was dirty, set the state of the cache line to

invalid. For a write-through cache,the writeback step is not required and this is eﬀectively a Cache Hit Invalidate operation. This cache operation is required and may be used by software to

invalidate a range of addresses from the data cache by stepping through the address range by the line size of the cache.In multiprocessor implementations with coherent caches, the operation

may optionally be broadcast to all coherent caches within the system.

D/T/S Hit Writeback (op=25,26,27):

If the cache block contains the speciﬁed address and it is

valid and dirty, write the contents back to memory. After the operation is completed,leave the state of the line valid, but clear the dirty state. For a write-through cache, this operation may be

treated as a nop.In multiprocessor implementations with coherent caches, the operation may optionally be broadcast to all coherent caches within the system.

I/D Fetch and Lock (op=28,29):

If the cache does not contain the speciﬁed virtual address, ﬁll

itfrom memory, performing a write-back if required.Setthe state to valid and locked.The way selected on a ﬁll from memory is implementation dependent. The lock state may be cleared

by executing an Index Invalidate,Index Writeback Invalidate, Hit Invalidate, or Hit Writeback Invalidate operation to the locked line, or via an Index Store Tag operation to the line that clears

the lock bit.It is implementation dependent whether a locked line is displaced as the result of an external invalidate or intervention that hits on the locked line. Software must not depend on the

locked line remaining in the cache if an externalinvalidate or intervention would invalidate the line if it were not locked.It is implementation dependent whether a Fetch and Lock operation

aﬀects more than one line. For example, more than one line around the referenced address may be fetched and locked.Itis recommended that only the single line containing the referenced

address be aﬀected.

It is implementation dependent whether the input address for an Index cacheop is converted into a physical address by the MMU, so to avoid the posibility of generating a TLB exception, the index value

should always be converted to an unmapped address (such as a kseg0 address by ORing the index with 0x80000000) before being used by the cache instruction. For example, the following code sequence

performs a data cache Index Store Tag operation using the index passed in GPR a0:

        li      a1, 0x80000000       /* Baseofkseg0 segment */
        or      a0, a0, a1           /* Convertindex to kseg0 address */
        cache   DCIndexStTag, 0(a1)  /* Performtheindex store tag operation */

Some CACHE/CACHEE operations may result in a Cache Error exception. For example, if a Writeback operation detects a cache or bus error during the processing of the operation, that error is reported

via a Cache Error exception.Also, a Bus Error Exception may occur if a bus operation invoked by this instruction is terminated in an error. However, cache error exceptions must not be triggered by

an Index Load Tag or Index Store tag operation, as these operations are used for initialization and diagnostic purposes.

It is implementation dependent whether a data watch is triggered by a cache instruction whose address matches the Watch register address match conditions. The preferred implementation is not to match

on the CACHE/CACHEE instructions.

The operation of the instruction is UNPREDICTABLE if the cache line that contains the CACHE instruction is the target of an invalidate or a writeback invalidate operation.

If this instruction is used to lock all ways of a cache at a speciﬁc cache index, the behavior of that cache to subsequent cache misses to that cache index is UNDEFINED.

The eﬀective address may be arbitrarily aligned. The CACHE/CACHEE instructions never causes an Address Error Exception due to a non-aligned address.

The CACHE instruction and the memory transactions which are sourced by the CACHE instruction, such as cache reﬁll or cache writeback, obey the ordering and completion rules of the SYNC instruction.

Any use of this instruction that can cause cacheline writebacks should be followed by a subsequent SYNC instruction to avoid hazards where the writeback data is not yet visible at the next level of the

memory hierarchy.

For multiprocessor implementations that maintain coherent caches, some of the Hit type operations

may optionally aﬀect all coherent caches within the implementation.In this case,if the eﬀective address uses a coherent Cache Coherency Attribute (CCA),

then the operation is globalized, meaning

it is broadcast to all of the coherent caches within the system.If the eﬀective address does not use one of the coherent CCAs, there is no broadcast of the operation.If multiple levels of caches are to

be aﬀected by one CACHE instruction, all of the aﬀected cache levels must be processed in the same manner - either all aﬀected cache levels use the globalized behavior or all aﬀected cache levels use

the non-globalized behavior.

Exceptions:

Address Error. Bus Error. Cache Error. Coprocessor Unusable. Reserved Instruction on NMS cores without caches. Reserved Instruction for CACHEE if EVA not implemented. TLB Invalid. TLB Reﬁll.