Encoding:

P32A

001000

rt

rs

1011001

100

111

111

6

5

5

7

3

3

3

Format: 

PRECEU.PH.QBLA rt, rs

DSP

Precision Expand Two Unsigned Bytes to Unsigned Halfword Values

Purpose:

Precision Expand Two Unsigned Bytes to Unsigned Halfword Values

Expand the precision of two unsigned integer byte values taken from the two left-alternate aligned positions of a quad byte vector to create four unsigned halfword values.

Description: 

rt = expand_prec8u16(rs31..24) || expand_prec8u16(rs15..8)

The two left-alternate aligned unsigned integer byte values from the four right-most byte elements in register rs are each expanded to unsigned halfword values and written to destination register rt. The precision expansion is achieved by pre-pending eight most-significant zero bits to the original byte v alue to generate each 16 bit unsigned halfw ord value.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

ValidateAccessToDSPResources()
tempB15..0 = 08 || GPR[rs]31..24
tempA15..0 = 08 || GPR[rs]15..8
GPR[rt]31..0 = tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled